mITX-BW – User Guide, Rev. 1.6
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// 44
Signal
Description
Power sequencing depends on LVDS panel selection. (Shared with eDP connector)
DDC CLK
DDC Channel Clock
Windows API will be available to operate the BKLTCTL signal. Some Inverters have a limited
voltage range 0- 2.5V for this signal: If voltage is > 2.5V the Inverter might latch up. Some
Inverters generate noise on the BKLTCTL signal, causing the LVDS transmission to fail
(corrupted picture on the display).
By adding a 1 k
Ω
resistor in series with this signal, mounted at the Inverter end of the cable
kit, the noise is limited and the picture is stable.
If the Backlight Enable is required to be active high then, check the following BIOS Chipset
setting: Backlight Signal Inversion = Enabled.
7.14.
Feature Connector (J13)
Figure 31: Feature Connector J13
Table 39: Pin Assignment J13
Pin
Signal
Type
Ioh / Iol
Pull U / D
Note
1
NC
I
/ 4 mA
2MΩ /
Pull-up to on-board Battery
2
SMBC
/ 4 mA
10kΩ /
Pull-up to +3V3Dual (+3V3 or SB3V3)
3
S4#
O
25 / 25 mA
4
SMBD
/ 4 mA
10kΩ /
Pull-up to +3V3Dual (+3V3 or SB3V3)
5
PWR_OK
O
25 / 25 mA
6
EXT_BAT
PWR
7
NC
I
8
NC
O
9
SB3V3
PWR
10
SB5V
PWR
11
GPIO0
IOT
12
GPIO1
IOT
13
GPIO2
IOT
14
GPIO3
IOT
15
GPIO4
IOT
16
GPIO5
IOT
17
GPIO6
IOT
18
GPIO7
IOT
19
GND
PWR
20
GND
PWR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
