KTD-N0882-I
Page 86
BIOS - Advanced
KTQ87/KTH81 Users Guide
Function
Selection
Description
Cache Request Length Limit
64 Bytes
128 Bytes
256 Bytes
512 Bytes
1Kbytes
2Kbytes
4Kbytes
8Kbytes
Request Length Limit. Determines the number of
bytes in the thread that the pre-fetchagent will
read for that thread.
Cache Request Count Limit
0, 1, … 3,
4
, 5, …, 15
Set the number of PCI cycle starts that have to
occur without a read hit on the completion data
buffer, before the cache data can be discarded.
Cache Timer Transfer Limit
0, 1, … 7,
8
, 9, …, 15
Number of PCI cycle starts that have to occur
without a read hit on the completion data
buffer, before the cache data can be discarded.
Cache Timer Lower Limit
0, 1,…
127
, … 4096
Minimum number of clock cycles that must have
passed without a read hit on the completion
data buffer, before the ‘cache miss limit’ check
can be triggered.
Cache Timer Upper Limit
0, 1,…
448
, … 4096
Discard cache data after this number of clock
cycles have passed without a read hit on the
completion data buffer.
Read Prefetch
Enabled
Disabled
Control the pre-fetch functionality on PCI
memory read transactions.
Completion Cache Mode
No Caching
Light Caching
Full Caching
Determines the rules for completing the caching
process.
Light caching:
All remaining read completion data will be
discarded after any of the data has been
returned to the PCI master.
Light & Full caching:
Pre-fetching is enabled.
All remaining read completion data will be
cached after data has been returned to the PCI
master and the PCI master terminated the
transfer with RETRY.
Full caching:
All remaining read completion data will be
cached after data has been returned to the PCI
master and the PCI master terminated the
transfer.
