Configuration
EBC2
Page 4 - 6
© 2005 Kontron Modular Computers GmbH
ID 29022, Rev. 01
26873
.02.VC.050120/135454
P R E L I M I N A R Y
Figure 4-7: JP11, JP13, JP14 and JP15 Jumpers
Figure 4-8: JP12, JP16, JP17 and JP18 Jumpers
4.2
V(I/O) Configuration
The EBC2 is configured for +3.3V V(I/O) operation and cannot be configured for +5V. Only uni-
versally coded or +3.3V coded PCI cards may be used with this board. The PCI connectors J13
and J14 are +3.3V key coded. Refer to sections 2.4.13 and 2.4.14 for orientation information
for PCI expansion boards.
4.3
LPC Address Mapping
The following table indicates the LPC address mapping for access to the digital input, digital
output, and POST code data.
The address map describes the offset location for the LPC I/O area. The LPC I/O address itself
is a function of the corresponding E²Brain™ module.
Table 4-2: LPC Address Mapping
REGISTER
LPC I/O ADDRESS OFFSET
DIN_DATA
0x0000 0000
DOUT_DATA
0x0000 0001
POST_CODE_DATA
0x0000 0080
JP13
JP11
JP14 JP15
JP16
JP12
JP17 JP18
