Software Setups
4-8
4.1.7 Chipset Features Setup
This part of the setup allows you to define chipset-specific options and features.
Option
BIOS
Defaults
Setup
Defaults
Possible
Settings
Description
CPU Internal Cache
Dis.
En.
En./Dis.
Enables or Disables the CPU Internal Cache (L1 cache).
External Cache
Dis.
En.
En./Dis.
Enables or Disables the External Cache (L2 cache).
CPU L2 Cache ECC
Checking
Dis.
En.
En./Dis.
Enables or Disables ECC Checking for L2 cache.
Note: processors provided by Kontron support ECC.
However, not all Pentium® II / III processors support ECC.
Check Intel’s website to know if your processor supports
ECC:
http://developer.intel.com/support/
processors/pentiumII/identify.htm.
SDRAM RAS-to-CAS
Delay
3 3
2,
3
Note: Upon boot-up, the BIOS will detect and display the optimal
value for the SDRAM options (first four options in this menu), if it
is different from the Setup value. You must enter the AWARD
Setup, and set the options at the suggested value if you want the
best performance.
This option inserts a timing delay between the CAS and RAS strobe
signals, used when SDRAM is written to, read from, or refreshed. The
number selected is the number of clocks to be inserted between a row
activate command and either a read or write command.
SDRAM RAS
Precharge Time
3 3
2,
3 Selects the number of CPU clocks for the RAS precharge. If an
insufficient number of cycles is allowed for the RAS to accumulate its
charge before SDRAM refresh, the refresh may be incomplete and the
DRAM may fail to retain data.
SDRAM CAS Latency
Time
3 3
2,
3 This option controls the number of clocks between when a read
command is sampled by the SDRAMs and when the chipset samples
read data from the SDRAMs. Select 3 for 3 DCLKs and 2 for 2 DCLKs.
If a given row is populated with a registered SDRAM DIMM, an extra
clock is inserted between the read command and when the chipset
samples read data.
SDRAM Precharge
Control
Dis. Dis. En./Dis. When Enabled, all CPU cycles to SDRAM result in an All Banks
Precharge Command on the SDRAM interface.
DRAM Data Integrity
Mode
Non-
ECC
ECC
ECC,
Non-ECC
When set to ECC, allows auto-correction of the data read from
memory. The ECC error flags’ status register and the error pointer are
updated if error correction occurs in this mode.
When set to Non-Ecc, no error checking or error reporting is done.
This option will work in ECC mode only if all installed memory banks
supports ECC (Error Checking and Correction)
Memory Hole At 15M-
16M
Dis. Dis. En./Dis. You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user information
of peripherals that need to use this area of system memory usually
discusses their memory requirements.
Video BIOS
Cacheable
Dis. En. En./Dis. Selecting Enabled allows caching of the video BIOS ROM at C0000h
plus the VGA BIOS size, resulting in better video performance.
However, in any program writes to this memory area, a system error
may occur.
Video RAM Cacheable
Dis.
En.
En./Dis.
When Enabled, video memory region is cacheable. Some off-board
video card drivers may behave strangely; in such a case, disable this
option.
8 Bit I/O Recovery
Time
3 1 1-8,
NA
16 Bit I/O Recovery
Time
2 1 1-4,
NA
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place because the
PCI bus is much faster than the ISA bus. These two fields let you add
recovery time (in bus clock cycles) for 8-bit and 16-bit I/O.
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