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Preface
CP6002
Page vi
ID 1036-6431, Rev. 2.0
P R E L I M I N A R Y
Status Register 0 (STAT0) ...............................................................4 - 7
Status Register 1 (STAT1) ...............................................................4 - 8
Control Register 0 (CTRL0) ............................................................4 - 9
Control Register 1 (CTRL1) ............................................................4 - 9
Device Protection Register (DPROT) ............................................4 - 10
Reset Status Register (RSTAT) ..................................................... 4 - 11
Board Interrupt Configuration Register (BICFG) ...........................4 - 12
Status Register 2 (STAT2) .............................................................4 - 13
Board ID High Byte Register (BIDH) .............................................4 - 13
4.4.10 Board and PLD Revision Register (BREV) ...................................4 - 14
4.4.11 Geographic Addressing Register (GEOAD) ..................................4 - 14
4.4.12 Watchdog Timer Control Register (WTIM) ....................................4 - 15
4.4.13 Board ID Low Byte Register (BIDL) ..............................................4 - 17
4.4.14 Debug LED Configuration Register (DLCFG) ...............................4 - 18
4.4.15 Debug LED Control Register (DLCTRL) .......................................4 - 19
IPMI Controller Status Register 0 (ICSTA0) ..................................4 - 20
IPMI Controller Status Register 1 (ICSTA1) ..................................4 - 21
IPMI Reset Status Register (IRSTA) .............................................4 - 22
IPMI Keyboard Controller Style Interface ......................................4 - 22
Power Considerations ............................................................. 5 - 3
CP6002 Baseboard .........................................................................5 - 3
Power Supply Units .........................................................................5 - 4
Start-Up Requirement .............................................................5 - 4
Power-Up Sequence ...............................................................5 - 4
Tolerance ................................................................................5 - 5
Regulation ...............................................................................5 - 5