886LCD/ATX(GV) -/ATXU(GV)
KTD-00647-C
Public User Manual
Date: 2007-02-08 Page
25 of 71
4.5 Parallel ATA harddisk interface
Two parallel ATA harddisk controllers are available on the board – a primary and a secondary controller.
Standard 3½” harddisks or CD-ROM drives may be attached to the primary and secondary controller board
by means of the 40 pin IDC connectors, IDE_P and IDE_S.
The harddisk controllers support Bus master IDE, ultra DMA 33/66/100 MHz and standard operation modes.
The signals used for the harddisk interface are the following:
DA*2..0
Address lines, used to address the I/O registers in the IDE hard disk.
HDCS*1..0#
Hard Disk Chip-Select. HDCS0# selects the primary hard disk.
D*15..8
High part of data bus.
D*7..0
Low part of data bus.
IOR*# I/O
Read.
IOW*# I/O
Write.
IORDY*#
This signal may be driven by the hard disk to extend the current I/O cycle.
RESET*#
Reset signal to the hard disk.
HDIRQ*
Interrupt line from hard disk.
CBLID*
This input signal (CaBLe ID) is used to detect the type of attached cable: 80-wire cable
when low input and 40-wire cable when 5V via 10Kohm (pull-up resistor).
DDREQ*
Disk DMA Request might be driven by the IDE hard disk to request bus master access to
the PCI bus. The signal is used in conjunction with the PCI bus master IDE function and
is not associated with any PC-AT bus compatible DMA channel.
DDACK*#
Disk DMA Acknowledge. Active low signal grants IDE bus master access to the PCI bus.
HDACT*#
Signal from hard disk indicating hard disk activity. The signal level depends on the hard
disk type, normally active low. The signals from primary and secondary controller are
routed together through diodes and passed to the connector FEATURE.
“*” is “A” for primary and “B” for secondary controller.
The pinout of the connectors are defined in the following sections.
