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Adjustments
5
Keysight 11683A Operating and Service Manual
39
FET Balance Adjustment
A characteristic of a FET Sampling Gate circuit is transient spikes caused by an imbalance in
gate-to-drain capacitance. The imbalance can be corrected by making the effective junction
capacitance equal. A capacitor of correct value is coupled across the gate-to-drain leads of the
active component with the lower junction capacitance. Other factors keep the transient from being
eliminated completely, therefore, the amplitude is reduced to a minimum.
Description
Adequate FET gate-to-drain capacitance balance is achieved when the transient spike amplitude
is found to be < 1.0 Vp-p at the appropriate test location (TP4 in the model 435A). Solder the
selected capacitor in place.
Equipment
The model 180C/1801A/1821A is the recommended oscilloscope for use in the balance
adjustment. An oscilloscope that meets or exceeds the critical specifications of
substituted.
Procedure
1
Remove the A3 assembly (refer to
“Disassembly of A3 sampling gate assembly”
Reinstall the LINE and A1 RANGE switch in the front panel before proceeding.
2
Connect the equipment as shown in
. (The oscilloscope probe will be coupled to TP4
if the 435A Power Meter is being used.)
3
Set the 11683A FUNCTION switch to STANDBY; the Power Meter RANGE switch to 3
μ
W.
4
Press the 435A ZERO Switch and check the spike amplitude on the oscilloscope display.
Remove A2C2 and replace it, in the same location, with the next higher value capacitor. A2C2
may be located in one of the two positions or it may be omitted; see
.
5
If the spike amplitude decreases, continue to increase the capacitor value, in sequence, until
the minimum spike amplitude (balance point) is found. The capacitor normally will not be >7 pF.
After two or three capacitors are tried, if the spike amplitude is constant or increases, a smaller
value capacitor may be tried. If the lowest value capacitor is reached without finding the
balance point, remove the capacitor and check the spike amplitude. Next begin to insert
capacitors, in sequence, in the other A2C2 location. When the spike amplitude of <1.0 Vp-p at
NOTE
This procedure normally will have to be performed only when the U1 assembly is replaced or if
the white/black or white/brown wires which connect A3A1 to A3J1 are moved since their relative
position is critical.
NOTE
The 435A ZERO switch must be pressed for the duration of this adjustment procedure.
Summary of Contents for 11683A
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