TM-281A
6
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Wide/Narrow Switching Circuit
The Wide port (pin 65) and Narrow port (pin 64) of the
MCU is used to switch between ceramic filters. When
the Wide port is high, the ceramic fi lter SW diodes (D501,
D502) cause CF501 to turn on to receive a Wide signal.
When the Narrow port is high, the ceramic fi lter SW di-
odes (D501, D502) cause CF502 to turn on to receive a Nar-
row signal. (See Fig. 3.)
Narrow
IC707 64pin
IF_IN
MIX_O
IC501
FM IC
CF502
(Narrow)
CF501
(Wide)
R505
R507
R506
R504
D501
D502
Wide
IC707 65pin
Fig. 3 Wide/Narrow switching circuit
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AF Signal System
The detection signal from the FM IC (IC501) goes to the
D/A converter (IC705) to adjust the gain and is output to the
AF fi lter (IC709) for characterizing the signal. The AF signal
output from IC709 and the DTMF signal, BEEP signal are
summed and the resulting signal goes to the D/A converter
(IC705). The AFO output level is adjusted by the D/A con-
verter. The signal output from the D/A converter is input to
the audio power amplifi er (IC715). The AF signal from IC715
switches between the internal speaker and the speaker jack
(J701) output. (See Fig. 4.)
AF
Filter
D/A
CONV.
D/A
CONV.
IC705
IC709
IC705
W/NO
(EVOL2)
AF PA
IC715
SP
FM IC
IC501
Fig. 4 AF signal system
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Squelch Circuit
The detection output from the FM IC (IC501) passes
through a noise amplifier (Q502) to detect noise. A volt-
age is applied to the MCU (IC707). The MCU controls the
squelch according to the voltage (SQIN) level. The signal
from the RSSI pin of IC501 is used for the S-meter. The
electric field strength of the receive signal can be known
before the SQIN voltage is input to the MCU, and the scan
stop speed is improved.
Q502
NOISE AMP
D503
IC501
IC707
FILOUT
RSSI
DET
MCU
FM IC
SQIN
RSSI
Fig. 5 Squelch circuit
PLL Frequency Synthesizer
The PLL circuit generates the fi rst local oscillator signal
for reception and the RF signal for transmission.
■
PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A
16.8MHz reference oscillator signal is divided at IC1 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output sig-
nal is buffer amplifi ed by Q9, then divided in IC1 by a dual-
module programmable counter. The divided signal is com-
pared in phase with the 5 or 6.25kHz reference signal in the
phase comparator in IC1. The output signal from the phase
comparator is fi ltered through a low-pass fi lter and passed
to the VCO to control the oscillator frequency. (See Fig. 6.)
■
VCO
Double the operating frequency is generated by Q6 in
transmit mode and Q4 in receive mode. The oscillator fre-
quency is controlled by applying the VCO control voltage,
obtained from the phase comparator, to the varactor diodes
(D4 and D6 in transmit mode and D3 and D5 in receive
mode). The TX/RX pin is set high in receive mode causing
Q7 and Q5 to turn Q6 off, and turn Q4 on. The TX/RX pin is
set low in transmit mode. The outputs from Q4 and Q6 are
amplifi ed by Q9 and sent to the RF amplifi ers through a 1/2
divider (IC2). (See Fig. 6.)
D4,D6
IC2
Q6
TX VCO
Q9
BUFF
AMP
D3,D5
Q4
RX VCO
Q5,Q7
T/R SW
1/2
divider
Charge
pump
LPF
Phase
comparator
1/M
1/N
5kHz/6.25kHz
5kHz/6.25kHz
REF
OSC
16.8MHz
PLL
DATA
IC1 : PLL IC
Q3
AMP
RF amplifiers
Q1,Q2
TX/RX (MCU)
Fig. 6 PLL circuit
CIRCUIT DESCRIPTION
