26
TK-980/981
Transmitter System
■
Outline
The transmitter circuit amplifies the desired frequency. It
FM-modulates the carrier signal by means of a varicap di-
ode.
■
Younger-stage circuit
The signal output from the VCO is amplified by a buffer
amplifier (Q7) and goes to the drive block. The younger-
stage circuit provides a stable drive output without a need
for adjustment. The APC circuit controls voltage in the
younger final stage (Q204).
■
VCO/PLL Circuit
The TK-980/981 has a common VCO for the transmitter
and the receiver in a sub-unit (A1). It is housed in a solid
shielded case and connected to the TX-RX unit (A/2) through
CN101. A filtered low-noise power supply is used for the
VCO and varicap diodes.
The VCO is described below. It is designed so that Q101
turns on with a prescribed frequency when a reverse bias is
applied to D100 and D101 by using the control voltage (CV)
through CN101. The control voltage is changed by turning
the trimmer capacitor (TC100). The output from Q103 is ap-
plied to the buffer amplifier (Q102) the output from Q102 is
applied to the doubler (Q100) to generate a VCO output sig-
nal. This signal is used as a drive input signal or a local signal
of the first mixer. Since a signal output from Q100 is input
to the PLL IC, it passes through CN101 and buffer amplifier
(Q300) and goes to the PLL IC (IC300). The modulation sig-
nal from CN101 is applied to D102 and passes through C106
and C107 to modulate the carrier.
The PLL IC uses a fractional N type synthesizer to im-
prove the C/N ratio and lock-up speed. The VCO output sig-
nal input to the pin 5 of the PLL IC is divided to produce a
comparison frequency according to a channel step. This sig-
nal is compared with the reference frequency which is out-
put from the VCXO (X1). VCXO provides 16.8MHz, 1.5ppm
(–30 to +60
°
C) and guarantees stable performance when
the temperature changes. The output signal from the phase
comparator passes through a charge pump and an external
active LPF (Q301, Q302) in the PLL IC to generate a DC VCO
control voltage CV. Serial data (DT, CK, EP) are output from
the CPU (IC511) and shift register (IC8) in the TX-RX unit (B/
2) to control the PLL IC. The PLL lock status is always moni-
tored by the CPU.
■
Unlock Circuit
During reception, the TR line goes high, the KEY line
goes low, and Q10 turns on. Q11 turns on and a voltage is
applied to the collector (8R). During transmission, the TR
line goes low, the KEY line goes high and Q13 turns on. Q12
turns on and a voltage is applied to 8T.
The CPU in the TX-RX unit (B/2) monitors the PLL (IC300)
LD line directly. When the PLL is unlocked during transmis-
sion, the PLL LD line goes low. The CPU detects this signal
and makes the KEY line low. When the KEY line goes low,
no voltage is applied to 8T, and no signal is transmitted.
Fig. 5
Transmitter system
CIRCUIT DESCRIPTION
IC504
IC3
Q101
IC711
MIC
AF AMP
TA75S01F
MIC KEY
INPUT
AF AMP,
IDC, LPF
TC35453F
IC511
CPU
30622M8A
-4F9GP
SUM AMP
TA75W558FU
X1
VCXO
16.8MHz
VCO
2SK508NV
(K52)
IC300
PLL
SA7025DK
Q102
RF AMP
2SC4226
(R24)
Q300
BUFFER
2SC4226
(R24)
Q202
RF AMP
2SC3356
(R24)
Q204
RF AMP
2SK2596
ANT
IC400
POWER AMP
M67760LC : TK-980
M67760HC : TK-981
Q7
BUFFER
2SC4226
(R24)
IC508
SHIFT
REG.
IC511
CPU
Q10
SW
Q11
SW
IC300
PLL
Q13
SW
Q12
SW
LD
TX-RX UNIT (B/2)
TR
8C
8R
8T
KEY
PLL lock
: LD “H”
Fig. 6
Unlock circuit
Q204
8T
POWER
AMP
IC400
APC
DRIVER
Q19
Q20
Q21
B
Q17
PRI
DRIVER
DC
AMP
CURR.
DET
DC
SW
DC
SW
LPF
D20
ANT SW
ANT
IC508
KEY
IC13
PC
IC6
(1/2)
R127
Fig. 7
APC circuit
■
Power Amplifier Circuit/Final
The transmit output signal from the VCO is amplified to a
specified level of the power module (IC400) by the drive
block (Q202, Q204). The amplified signal goes to a low-pass
filter. The low-pass filter removes unwanted high-frequency
harmonics. The resulting signal passes through the trans-
mission/reception selection diode (D208), then goes to the
antenna terminal.
■
APC Circuit
The direct current that flows through the final module
(IC400) produces a voltage across resistors R127. This volt-
age is applied to pin 6 of IC13 (2/2), and is input as the refer-
ence voltage difference of pin 5 and amplified.
