25
TK-860G/862G
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Wide/Narrow Changeover Circuit
The W/N port (pin 4) of the shift register (IC510) is used
to switch between ceramic filters. When the W/N port is
high, Q4 turns on and the ceramic filter SW diode (D8, D10)
CF1 turns on to receive a Narrow signal. At the same time,
Q35 turns on and one of the filters is selected so that the
wide and narrow audio output levels are equal.
When the W/N port is low, Q3 turns on and the ceramic
filter SW diode (D8, D10) CF2 turns on to receive a Wide
signal.
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AF Signal System
The detection signal (DEO) from the TX-RX unit goes to
the audio processor (IC508) of the control unit. The signal
passes through a filter in the audio processor to adjust the
gain, and is output to IC507. IC507 sums the AF signal and
the DTMF signal, BEEP signal and returns the resulting sig-
nal to the TX-RX unit. The signal (AFO) sent to the TX-RX
unit is input to the D/A converter (IC6). The AFO output level
is adjusted by the D/A converter. The signal output from the
D/A converter is input to the audio power amplifier (IC13).
The AF signal from IC13 switches between the internal
speaker and speaker jack (J1) output.
■
Squelch Circuit
The detection output from the FM IF IC (IC5) passes
through a band-pass filter and a noise amplifier (Q10) in the
control unit to detect noise. A voltage is applied to the CPU
(IC502). The CPU controls squelch according to the voltage
(ASQ) level. The signal from the RSSI pin of IC5 is moni-
tored. The electric field strength of the receive signal can be
known before the ASQ voltage is input to the CPU, and the
scan stop speed is improved.
FIg. 4
AF signal system
Fig. 5
Squelch circuit
CIRCUIT DESCRIPTION
Fig. 3
Wide/Narrow changeover circuit
CF1
(Narrow)
CF2
(Wide)
IFI
MXO
IC5
IF system
AFO
DET
OUT
C70
C72
C53
R19
R23
R46
R32
R30
R39
R38
+
+
Q35
8RC
Q37
R59
W/N
IC510 4pin
Wide : L
Narrow : H
C51
D8
D10
Q3
5C
Q4
Wide : H
Narrow : L
AUDIO
PROCE.
SUM
AMP
D/A
CONV.
IC508
IC507
IC6
AF PA
IC13
SP
DTMF
AFO
DEO
CONTORL UNIT
Q10
NOISE AMP
D11
IC4
IC5
IC502
AF
RSSI
BPF
DET
CPU
IF
SYSTEM
CONTROL UNIT
ASQ
RSSI
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal
for reception and the RF signal for transmission.
■
PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A
16.8MHz reference oscillator signal is divided at IC3 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output sig-
nal is buffer amplified by Q106 (Sub-unit), then divided in IC3
by a dual-module programmable counter. The divided signal
is compared in phase with the 5 or 6.25kHz reference signal
in the phase comparator in IC3. The output signal from the
phase comparator is filtered through a low-pass filter and
passed to the VCO to control the oscillator frequency. (See
Fig. 6)
■
VCO
The TK-860G/862G has VCO in a Sub-unit (A1) housed in
a solid shielded case and connected to the TX-RX unit
through CN101.
The operating frequency is generated by Q103 in trans-
mit mode and Q101 in receive mode. The oscillator fre-
quency is controlled by applying the VCO control voltage,
obtained from the phase comparator, to the varactor diodes
(D102 and D104 in transmit mode and D101 and D103 in
receive mode). The RX (ST) pin is set low in receive mode
causing Q102 to turn Q103 off, and turn Q101 on. The RX
(ST) pin is set low in transmit mode. The outputs from Q101
and Q103 are amplified by Q106 and sent to the buffer am-
plifiers.
