6
TK-3130/3131
CIRCUIT DESCRIPTION
PLL System
■
VCO Circuit
The VCO is housed in a shield case.
The VCO circuit consists of a transistor (Q4), a variable
capacity diode (D4) for frequency control, a variable capacity
diode (D8) for modulation, transmit/receive frequency shift
diode (D17), control transistor (Q2), variable capacitor (TC1)
for PLL lock voltage control, and oscillator buffer amplifier
(Q5).
■
PLL Circuit
Frequency data is sent to the PLL IC (IC1) from the CPU
(IC204) as serial data when the power turns on, when the
channel is changed, or when transmission begins. It sets
the variable divider in the PLL IC.
The TCXO (X1) produce a 12.8MHz reference frequency.
It is divided to produce a 12.5kHz PLL comparison fre-
quency in the PLL IC.
The VCO input is divided by the divide ratio set by the
divider in the PLL IC to generate 12.5kHz. It is compared
with the reference comparison frequency by the phase
comparator to detect a phase difference.
The charge pump circuit in the PLL IC converts it to a
control voltage that can drive the VCO directly.
The control voltage passes through a loop filter which
passes low frequency and is applied to the VCO control pin
to control the oscillator frequency. The loop filter removes
unwanted harmonics and noise contained in the output from
the phase comparator and determines PLL response and
synchronizing characteristics by the amplitude and phase
characteristics (Fig. 8).
Fig. 7
VCO circuit
In receive mode, the shift signal T/R goes low, Q2 turns
off, and the shift diode (D17) not contact. Q4 produces the
first local frequency for reception.
(Receive channel frequency – 38.85MHz)
In transmit mode, the shift signal T/R goes high, Q2 turns
on and D17 does conducts. Q4 produces about 460~470
MHz and the VCO frequency equals the transmit channel
frequency.
The 3.0V circuit voltage is produced by ripple removing
filter circuit Q3.
■
Unlock Detection Circuit
If the PLL cannot be synchronized for some reason or
other when switching the channel or changing between
transmission and reception, the PLL IC outputs a low unlock
detection signal. This signal goes to the CPU to inhibit trans-
mission when the PLL is unlocked.
Fig. 8
PLL circuit
+
+
+
CP1
XIN
3C
3C
PLL data
(CPU)
STB
DATA
CK
CPU (IC204)
UL
VCO
LV
Loop filter
VCO OUT
F OUT
FIN1
3C,T/R,MOD
PLL IC
IC1
LD
TCXO
TO
X1 12.8MHz
Vcont
R22
R23
R126
R21
R24
R26
C42
C186
C27
C38
C36
C198
C194
TC1
D8
D4
D17
C44
C46
C30
C31
C29
C33
C32
D3
R15
R17
R36
L10
L9
L43
Q4
Q2
Q3
Q5
C45
C41
R25
C185
R35
R18
R10
L11
R11
L8
L44
L12
R14
R146
LV
MOD
T/R
3C
+
VCO
OUT
