TK-290-11B
3
CIRCUIT DESCRIPTION
1. PLL Frequency Synthesizer
The frequency synthesizer consists of the VCXO (X1),
VCO (L800), PLL IC (IC5) and buffer amplifiers. The VCXO
generates a 16.8MHz signal. The frequency stability is within
±
2.0ppm (temperature range of –30 to +60
°
C).
The frequency tuning and modulation of the VCXO are
done to apply a voltage to pin 1 of the VCXO. The output of
the VCXO is applied to pin 9 of the PLL IC.
The VCO of the TK-290 covers the 38MHz spread, setting
frequencies in r1, r2 (receive) and t1, t2 (transmit) with a bias
voltage applied to the –V terminal of the VCO.
A zero (0) volt bias is applied at frequencies lower than r1,
t1. Frequencies r1, t1 through r2, t2 are biased with –3 volts.
Frequencies higher than r2, t2 are biased with –6 volts, and at
174MHz to 178MHz are biased with –9 volts.
The relation of VCO frequency versus PLL lock voltage is
shown in Figure 2.
The output of the VCO is amplified by the buffer amplifier
(Q14) and doubled by Q3, and is then routed to pin 6 of the
PLL IC. The output of the VCO is also amplified by the buffer
amplifier (Q5) and is routed to the next stage according to the
T/R switch (D602, D603).
The PLL IC consists of a prescaler, fractional divider, refer-
ence divider, phase comparator and charge pump. This PLL
IC is a fractional-N type synthesizer and performs in the 80 or
100kHz reference signal which is one eighth of the channel
step (2.5 or 3.125 kHz). The input signal from pin 6 of the PLL
IC is divided down to 80 or 100kHz and compared at the
phase comparator. The pulsed output signal of the phase
comparator is applied to the charge pump and transformed
into a DC signal in the loop filter (LPF). The DC signal is ap-
plied to pin 4 of the VCO and is locked to keep the VCO fre-
quency constant.
PLL data is output from DT (pin 85), CLK (pin 84) and LE
(pin 93) of the microprocessor (IC406). The data is input to
the PLL IC when the channel is changed or when transmis-
sion is changed to reception and vice versa. A PLL lock con-
dition is always monitored by pin 30 (UL) of the microproces-
sor. When the PLL is unlocked, the UL goes low.
r1
t1
r2
t2
174
CV voltage
Frequency
(MHz)
178
136
IC6
L800
VCO
CV
IC5
PLL
LPF
DT,CLK,LE
CPU
IC406
Q5
D602,603
Q14
Q3
X1
–VC
–V
VCXO
BUFF
SW
BUFF
DOUBLER
BPF
to drive amp
to mixer
UL
IC3
IC604
FC
TO
Fig. 1
PLL block diagram
Fig. 2
CV voltage vs frequency
