Keithley PIO-96, Instruction Manual

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PIO-96 User’s Manual I/O Address Map B-3
Data ports
The PA and PB ports of the 8255 chip are byte-wide, and the direction of all lines within a port
is set by the control register. The PC Port of the 8255 chip may also be used as a byte-wide port
or split into two ports of four bits (nibble-wide). The PC0 to PC3 lines are known as the PC-
lower port and the PC4 to PC7 lines are known as the PC-upper port. The directions of the PC-
upper and PC-lower ports are independently programmable. In modes 1 and 2 of PPI operation,
the PC port assumes the role of a control or “handshaking” port and many of its lines assume
fixed functions. However, in Mode 0 (basic input/output), the PC lines behave exactly as the PA
and PB ports so that you have three independent 8 bit ports for a total of 24 digital I/O lines.
There are slight electrical differences between the ports. Although all three ports are TTL/
CMOS-compatible, the PB and PC Ports are designed also to source current as high as 1mA at
1.5V for driving resistive loads or Darlington type power transistors, etc. The PA port does not
have this capability. For dissipation reasons, no more than eight outputs total should be used in
current sourcing applications. The port descriptions for each 8255 chip are as follows:
•
Port A - Consists of one 8 bit data output latch/buffer and one 8 bit data input latch.
• Port B - Consists of one 8-bit data input/output latch/buffer and one 8-bit data input buffer.
•
Port C - Consists of one 8-bit data output latch/buffer and one 8-bit data input buffer (no
latch for input). This port can be divided into two 4 bit ports under the mode control. Each 4
bit port contains a 4 bit latch and it can be used for the control signal outputs and status sig-
nal inputs in conjunction with ports A & B (modes 1 & 2).]
Control port
The control port bits on each 8255 chip are used as shown in Table B-2.
Table B-2
Control register bit functions for each 8255 chip
Control
group Bit
number
Function
I/O status for this bit
1
When bit value = 0 When bit value = 1
Bit 7 Mode set flag Inactive Active
A Bit 6 Mode selections for the PA
and the PC-upper ports When bit 6 = 0 AND bit 5 = 0: Mode 0
When bit 6 = 0 AND bit 5 = 1: Mode 1
When bit 6 = 1 AND bit 5 = 0: Mode 2
When bit 6 = 1 AND bit 5 = 1: Mode 2
Bit 5
Bit 4 I/O direction for the PA port Outputs, all bits of
this port. Inputs, all bits of
this port.
Bit 3 I/O direction to the PC-upper
port Outputs, all bits of
this port. Inputs, all bits of
this port.
B Bit 2 Mode selections for the PB
and the PC-lower ports Mode 0 Mode 1
Bit 1 I/O direction for PB port Outputs, all bits of
this port. Inputs, all bits of
this port.
Bit 0 I/O direction for the
PC-lower port Outputs, all bits of
this port. Inputs, all bits of
this port.
1
For safety, the values of bits 0, 1, 3, and 4 default to “1” upon computer power-up or reset, so that all ports start out as
inputs.