5-2
Programming
General
The PIO-24 emulates the Intel 8255 PPI Control Word Mode 0. On power up or
whenever the PC Bus RESET line is asserted, all ports are initially set up in the Input
Mode.
The PA and PB Ports are byte-wide, and the direction of all lines within a port is
set by the Control Register. The PC Port can also be used as a byte-wide port, or it can
be split into two ports of four bits (nibble wide). The PC0-3 Lines are known as
PC-
Lower
, and the PC4-7 Lines as
PC-Upper
. Directions of the PC Upper and Lower
ports are independently programmable. Detailed port descriptions are as follows:
•
Port A — Consists of one 8-bit data output latch/buffer and one 8-bit data
input latch.
•
Port B — Consists of one 8-bit data output latch/buffer and one 8-bit data
input buffer.
•
Port C — Consists of one 8-bit data output latch/buffer and one 8-bit data
input buffer. This port can be divided into two 4-bit ports under the Mode
Control.
Control Byte
At power-up or after a system reset, all PIO-24 lines are configured as inputs. The
Control Byte is an 8-bit (byte) hexadecimal number used to configure the direction of
the PIO-24 ports: PA, PB, PC (lines 0-3) and PC (4-7). The controlling PIO-24 soft-
ware program must output the Control Byte to the PIO-24 to change the directions
(input or output) of the ports. It is important to note that there is one byte to control
four ports and that when a port is initialized as an output port its lines are in a reset
state. The Control Byte is output to the PIO-24 address location at base 3.
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