5-4
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KPXI-CON-900-01 Rev. A / January 2007
Section 5: Utilities
KPXI System Controller User’s Manual
GPIO control registers
There are three GPIOs on the Model KPXI-CON controller related to the watchdog timer. They are
listed as follows. The GPIO control base port is 480H.
WDT_TOUT# pin selection
The WDT_TOUT# signal is multiplexed with GPIO32. When using WDT, this signal must be
switched to WDT_TOUT# function. It uses bit 0 of GP 30H to set WDT_TOUT function.
(0 = WDT_TOUT#, 1 = GPIO32)
RESET hardware circuit selection
GPO24 of the 6300ESB is designed to control the reset circuit. When GPO24 is low, the system
will reset according to the level of the WDT_TOUT# signal. When GPO24 is high, the system will
not be reset by WDT_TOUT#. Set bit 24 of GP 04H to 0 for output use. Bit 24 of
GP 0CH determines the level of GPO24 (0 = Low, 1 = High). A setting already exists in
the BIOS setup menu. The user can set this item before programming WDT. For information on
changing BIOS settings see
WDT LED Control
GPO25 of the 6300ESB is designed to control WDT LED. Two features of the WDT LED are
supported on Model KPXI-CON controller. WDT LED lights or blinks.
WDT LED lights:
Set bit 25 of GP 04H to 0. Bit 24 of GP 0CH determines the
state of WDT LED. (0 = light, 1= dark)
WDT LED blinks:
Set bit 25 of GP 04H to 0. Bit 25 of GP 18H enables WDT
LED blinking function. (0 = function normally, 1 = enable blinking) The high and low times have
approximately 0.5 seconds each.
WDT programming procedure
Step 1:
Set BIOS Setting in Integrated Peripherals\Onboard Device Page Watch Dog Timer Item
to
Enabled
.
Step 2:
Make sure WDT_TOUT# signal is functional (not GPIO32 function).
Step 3:
Set WDT output enable, presecaler and interrupt type into WDT configuration register.
Step 4:
Obtain control base from Base Address register.
Step 5:
Program Preload register’s value according to unlocking sequence.
Step 6:
Set WDT timer mode into WDT Lock Register.
Step 7:
Enable WDT from WDT Lock register and program the functionality of WDT LED.
Step 8:
To prevent the timer from causing an interrupt or driving WDT_TOUT#, the timer must be
reloaded periodically. The frequency of reloads required is dependent on the value of the
preload values. To reload the down-counter, the register unlocking sequence must be
performed.
Step 9:
If the user wishes to disable WDT, set bit 1 of WDT lock Register to 0.
W83627HF (Super IO) watchdog timer
The W83627HF watchdog timer circuit is implemented in a programmable logic device. The
watchdog timer contains a "Control and Status Register." The register allows the BIOS or user
application to determine if a watchdog time out was the source of a particular reset. The timeout
Summary of Contents for KPXI
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