Model 6487 Reference Manual
Status Structure
10-13
Measurement event status
The used bits of the measurement event register (
) are described as follows:
•
Bit B1, low limit 1 fail (LL1F)
— Set bit indicates that the low limit 1 test has
failed.
•
Bit B2, high limit 1 fail (HL1F)
— Set bit indicates that the high limit 1 test has
failed.
Figure 10-6
Measurement event status
ROF
(B7)
LP
(B5)
HL2F
(B4)
LL2F
(B3)
HL1F
(B2)
OR
BFL = Buffer Full
BAV = Buffer Available
ROF = Reading Overflow
RAV = Reading Available
LP = Limits Pass
IOV = Input Overvoltage
& = Logical AND
OR = Logical OR
&
&
&
&
&
(B0)
&
128
(2
7
)
32
(2
5
)
16
(2
4
)
8
(2
3
)
4
(2
2
)
2
(2
1
)
Decimal
Weights
RAV
(B6)
[:EVENt]?
64
(2
6
)
BFL
(B9)
BAV
(B8)
&
&
&
LL1F
(B1)
ROF
(B7)
LP
(B5)
HL2F
(B4)
LL2F
(B3)
HL1F
(B2)
Measurement
Condition
Register
(B0)
RAV
(B6)
(B15)
:CONDition?
BFL
(B9)
BAV
(B8)
LL1F
(B1)
Measurement
Event Register
ROF
(B7)
LP
(B5)
HL2F
(B4)
LL2F
(B3)
HL1F
(B2)
(B0)
RAV
(B6)
BFL
(B9)
BAV
(B8)
LL1F
(B1)
512
(2
9
)
256
(2
8
)
HL2F = High Limit 2 Fail
LL2F = Low Limit 2 Fail
HL1F = High Limit 1 Fail
LL1F = Low Limit 1 Fail
INT = Interlock Asserted
VSC = Voltage Source Compliance
:ENABle <NRf>
:ENABle?
Measurement
Event Enable
Register
To MSB
bit of Status
Byte Register
IOV
(B10)
&
INT
(B11)
(B12)
VSC
(B14)
&
&
(B13)
(B15)
IOV
(B10)
INT
(B11)
(B12)
VSC
(B14) (B13)
(B15)
IOV
(B10)
INT
(B11)
(B12)
VSC
(B14) (B13)
1024
(2
10
)
2048
(2
11
)
16384
(2
14
)
