Model 6487 Reference Manual
Limit Tests and Digital I/O
8-9
Category register component handler
When using this type of handler, the Model 6487 sends a bit pattern to three handler lines
when a pass or fail condition occurs. This bit pattern determines the bin assignment for the
DUT. With the pass/fail pattern on the output, line #4 is then pulsed. This EOT (end-of-
test) pulse latches the bit pattern into the register of the handler, which places the DUT in
the assigned bin. When interfacing to this type of handler, a maximum of eight component
handler bins are supported.
If the handler requires a low-going EOT pulse, line #4 of the digital output must initially
be set high. When the EOT line is pulsed low, the binning operation occurs. When using
the CONFIG LIMITS MENU to define pass/fail bit patterns, line #4 must be set low. If,
for example, the required fail pattern by the handler is HI, LO, HI, then you must define
the fail pattern of the test to be HI, LO, HI, LO. When the test fails, the HI, LO, HI bit pat-
tern is sent to the handler. When line #4 goes LO, the bit pattern is latched into the register
of the handler and the binning operation occurs.
Conversely, if the handler requires a high-going EOT pulse, the EOT line of the digital
output must initially be set low (off). When the EOT line is pulsed high, the binning oper-
ation occurs.
Line 4 mode
When using a category pulse component handler, the Model 6487 must be set to the Busy
or /Busy mode. In the Busy mode, the idle state for line 4 is LO. When the test starts (SOT
line pulsed), line 4 goes HI (busy state). After the test is finished, it goes back to LO. For
the /Busy mode, the idle state for line 4 is HI and busy state is LO.
When using a catagory register component handler, the Model 6487 must be set for the
End of Test mode. In this mode, the Model 6487 sends the EOT pulse to the component
handler as previously explained.
