JYTEK PCIe-69852, User Manual

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12
D15 D14 D13 D12 …� D3 D2 D1 D0
D15 ~ D2 bits represent the data from ADC (2’s complement)
D1, D0 bits are always 0
Table 3-1: Input Range and Data Format
Description Full scale range Least significant
bit
FSR-1LSB -FSR
Bipolar Analog
Input ±10V 1.22mV 9.99878V -10.000V
±2V 0.244mV 1.99976V -2V
±0.2V 24.4uV 0.199976V -0.2V
Digital Code N/A N/A 7FFC 8000
Table 3-2: Input Range FSR and –FSR Values
Description Mi1LSB Midscale Midscale -1LSB
Bipolar Analog
Input ±10V 1.22mV 0V -1.22mV
±2V 0.244mV 0V -0.244mV
±0.2V 24.4V 0V -24.4μV
Digital Code 0004 0000 FFFC
Table 3-3: Input Range Midscale Values
3�2�3 DMA Data Transfer
The PXIe-69852, a PCIe Gen 2 X 4 device, is equipped with a 200MS/s high sampling rate ADC,
generating a 800 MByte/second rate.
To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data
streaming, as it helps to achieve full potential PCI Express bus bandwidth. The bus-mastering
controller releases the burden on the host CPU since data is directly transferred to the host memory
without intervention. Once analog input operation begins, the DMA returns control of the program.
During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO,
and then transfers the data to a user-defined DMA buffer in the computer.
Using a high-level programming library for high speed DMA data acquisition, the sampling period
and the number of conversions needs simply to be assigned into specified counters. After the AD
trigger condition is met, the data will be transferred to the system memory by the bus-mastering
DMA.
In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or other, it is difficult to
allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with
scatter-gather function to link non-contiguous memory blocks into a linked list so users can transfer
large amounts of data without being limited by memory limitations. In non-scatter-gather mode, the
maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there
is no limitation on DMA data transfer size except the physical storage capacity of the system.
Users can also link descriptor nodes circularly to achieve a multi- buffered DMA. Figure 3-2 illustrates
a linked list comprising three DMA descriptors. Each descriptor contains a PCI address, PCI dual
address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address