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3�6 ADC Timing Control
3�6�1 Timebase Architecture
ADC
X6
Multiplier
PLL
For ADC
State machine
For ADC
Data Bus
80MHz
480MHz
FPGA
ADC Output
80MHz
Onboard
80MHz
Oscillator
Figure 3-12: PCIe-69814 Timebase Architecture
3.6.2 Basic Acquisition Timing
The PCIe-69814 commences acquisition upon receipt of a trigger event originating with
software command, external digital trigger. The Timebase is a clock provided to the ADC
and acquisition engine for essential timing. The Timebase is from an onboard synthesizer.
To achieve different sampling rates, a scan interval counter is used.
Using the post-trigger mode as an example, as shown, when a trigger is accepted by the
digitizer, the acquisition engine commences acquisition of data from ADC, and stores the
sampled data to the onboard FIFO. When FIFO is not empty, data will be transferred to
system memory immediately through the DMA engine. The sampled data is generated
continuously at the rising edge of Timebase according to the scan interval counter setting.
When sampled data reaches a specified value, in this example 256, acquisition ends.
TIMEBASE
DATA
D1
D253 D254
Acquisition
In Progress
Trigger
Acquisition initiates following this clock edge
D2
5
5
2
D
4
D
3
D
D256
Analog
signal
Trigger mode = post-trigger, DataCnt = 256, ScanIntrv = 1
Figure 3-13: Basic Digitizer Acquisition Timing
