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46

Operation Theory

computer’s memory via DMA, and will occupy the PCI

bandwidth.
If the value specified in UC_counter is smaller than the sample

size of the waveform patterns, the waveform will be generated

piece-wisely. For example, if you defined a 16-sample sine

wave and set the UC_counter to 2, the generated waveform

will be a 1/8-cycle sine wave for every waveform period, and a

complete sine wave will be generated for every 8-iterations. If

you specified a UC_counter value that is larger than the

sample size of the waveform LUT (for example, 32), the

generated waveform will be a 2-cycle sine wave for every

waveform period.

Figure 4-16: Finite Iterative Waveform Generation with Post-trigger

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Summary of Contents for NuDAQ PCI-69222

Page 1: ...Advance Technologies Automate the World Manual Rev 1 00 Revision Date May 30 2017 NuDAQ PCI 69222 NuDAQ PCI 69223 16 bit High Performance DAQ Card with Programmable Function I O User s Manual...

Page 2: ...nual is organized This manual is organized as follows Chapter 1 Introduction This chapter introduces the JYTEK NuDAQ PCI 69222 and NuDAQ PCI 69223 cards including their features specifications softwar...

Page 3: ...throughout the man ual to make sure that you perform certain tasks and instructions properly NOTE Additional information aids and tips that help you per form particular tasks IMPORTANT Criticalinform...

Page 4: ......

Page 5: ...ssignment 13 CN1 Pin Assignment 14 CN2 Pin Assignment 16 CN1 CN2 Signal Descriptions 17 SSI Connector Pin Assignment 18 SSI Connector Signal Description 19 2 3 Analog Input Signal Connection 20 Types...

Page 6: ...Programmable Function I O 48 TTL DI DO 48 General Purpose Timer Counter 49 Basic Timer Counter Functions 49 General Purpose Timer Counter Modes 50 Digital Waveform Acquisition and Generation 56 4 5 Is...

Page 7: ...17 Table 2 5 SSI Connector Pin Assignment 18 Table 2 6 SSI Connector Signal Description 19 Table 4 1 Bipolar Analog Input Range and Output Digital Code 29 Table 4 2 Bipolar Analog Input Range and Outp...

Page 8: ...7 Gated Trigger with Finite Scan Acquisition 36 Figure 4 8 Scatter gather DMA for Data Transfer 38 Figure 4 9 FIFO Data In Out Structure 40 Figure 4 10 Waveform Generation for Three Channels Update 4...

Page 9: ...igure 4 30 Encoder Isolation Input Module 58 Figure 4 31 Encoder OGRx Input 59 Figure 4 32 CW CCW Encoder Timing 59 Figure 4 33 X1 Encoder Mode 60 Figure 4 34 X2 Encoder Mode 60 Figure 4 35 X4 Encoder...

Page 10: ...vi...

Page 11: ...variety of applications including TTL digital I O high speed DIO general purpose timer counter and PWM output These cards analog input analog output and function I O are capable of functioning simult...

Page 12: ...H TTL DI and 16 CH TTL DO 2 MHz 32 CH high speed DIO 4 CH 32 bit 80 MHz general purpose timer counter 4 CH PWM outputs 2 CH 4 MHz dedicated encoder inputs supporting AB phase and CW CCW Four DMA chann...

Page 13: ...250 mV Operational common mode voltage range 8 V Overvoltage protection Power on Power off Continuous 30 V Continuous 30 V Continuous 30 V Continuous 30 V FIFO buffer size 1K samples Data transfers Pr...

Page 14: ...ction 23 C 5 C Number of channels 2 D A converter DAC8812 or equivalent Maximum update range 1M sample s static Resolution 16 bit FIFO size 512 samples 2 CH sharing Data transfers Programmed I O DMA O...

Page 15: ...gic low VOL 0 5 V max IOL 10 mA max Logic high VOH 2 6 V min IIH 10 mA max Supported modes4 16 CH TTL DI and16 CH TTL DO 4 CH 32 bit general purpose timer counters Clock source Internal or External Ma...

Page 16: ...liant Dimension 120 mm x 87 mm I O connector 2 x 68 pin female VHDCI connectors Power requirement typical 5 VDC 1 2A 12 VDC 760 mA 12 VDC 50 mA Operating environment Ambient temperature 0 C to 45 C Re...

Page 17: ...t work at the same time Refer to section 4 3 and 4 4 5 Refer to Chapter 4 Input Range System Noise 10 V 0 78 LSBrms 5 V 0 80 LSBrms 2 5 V 0 98 LSBrms 2 V 0 96 LSBrms 1 25 V 0 77 LSBrms 1 V 0 81 LSBrms...

Page 18: ...be protected from static discharge and physical shock Never remove any of the socketed parts except at a static free workstation Use the anti static bag shipped with the product to handle the card Wea...

Page 19: ...DAQPilot is a driver and SDK with a graphics driven interface for various application development environments DAQPilot comes as JYTEK s commitment to provide full support to its comprehensive line o...

Page 20: ...DAQMaster is a smart device manager that opens up access to JYTEK data acquisition and test and measure ment products DAQMaster delivers all in one configurations and provides you with a full support...

Page 21: ...supe rior performance and reliability from your data acquisition sys tem DASK kernel drivers now support the revolutionary Windows Vista OS Figure 1 4 Legacy Software Support Overview NOTE JYTEK stro...

Page 22: ...ws Vista 32 bit or 64 bit editions Supports AMD64 and Intel x86 64 architectures Digitally signed for Windows Vista 64 bit edition Utilizes WOW64 subsystem to ensure that 32 bit applications run norma...

Page 23: ...69223 Layout 2 2 Connector Pin Assignment The PCI 69222 PCI 69223 card is equipped with two VHDCI 68 pin connectors CN1 is for analog input output while CN2 is for digital input output and encoder fu...

Page 24: ...5 AI6 AIH6 28 62 AI14 AIL6 AI7 AIH7 27 61 AI15 AIL7 AGND 26 60 AISENSE NC 25 59 NC NC 24 58 NC NC 23 57 NC NC 22 56 NC NC 21 55 NC NC 20 54 NC NC 19 53 NC NC 18 52 NC AGND 17 51 AGND AO0 16 50 AGND AO...

Page 25: ...E AI8 AIH8 25 59 AI24 AIL8 AI9 AIH9 24 58 AI25 AIL9 AI10 AIH10 23 57 AI26 AIL10 AI11 AIH11 22 56 AI27 AIL11 AI12 AIH12 21 55 AI28 AIL12 AI13 AIH13 20 54 AI29 AIL13 AI14 AIH14 19 53 AI30 AIL14 AI15 AIH...

Page 26: ...GPI7 GPTC_AUX1 27 61 GPI15 GPTC_AUX3 DGND 26 60 DGND GPO0 GPTC_OUT0 25 59 GPO8 GPO1 GPTC_OUT1 24 58 GPO9 GPO2 GPTC_OUT2 23 57 GPO10 GPO3 GPTC_OUT3 22 56 GPO11 GPO4 21 55 GPO12 GPO5 20 54 GPO13 GPO6 19...

Page 27: ...pair marked as AIH 0 7 and AIL 0 7 PCI 69223 Analog Input Channels 0 31 Each channel pair AI i i 16 I 0 15 can be configured as either two single ended inputs or one differential input pair marked as...

Page 28: ...ND Input GPTC 0 3 gate GPTC_OUT 0 3 DGND Output GPTC 0 3 output GPTC_UD 0 3 DGND Input GPTC 0 3 up down NC NC NC No connection Definition Pin Definition RESERVED 1 2 DGND SSI_ADCONV 3 4 DGND SSI_DAWR...

Page 29: ...ADCONV signal SSI_AD_TRIG Master Output Sends the internal AD_TRIG out Slave Input Accepts the SSI_AD_TRIG as the digital trigger signal SSI_DAWR Master Output Sends the DAWR out Slave Input Accepts t...

Page 30: ...ngle Ended RSE Non Referenced Single Ended NRSE and Differential Input DIFF Types of Signal Sources Floating Signal Sources A floating signal source means it is not connected in any way to the buildin...

Page 31: ...the grounding point The external analog input signal provides its own reference grounding point and is suitable for ground referenced signals Referenced Single ended RSE Mode In referenced single end...

Page 32: ...and NRSE Input Connections Differential input mode The differential input mode provides two inputs that respond to signal voltage difference between them If the signal source is ground referenced the...

Page 33: ...equiv alent source impedance If the source impedance is less than 100 ohms you can simply connect the negative side of the signal to AIGND as well as the negative input of the instrumentation amplifie...

Page 34: ...24 Hardware Information...

Page 35: ...care fully inspect the module for any damage Press down all socketed ICs to make sure that they are properly seated Do this only with the module placed on a firm flat surface WARNING Do not apply pow...

Page 36: ...by the system Configuration The card configuration is done on a card by card basis for all PCI cards on your system Because configuration is controlled by the system and the software there is no jumpe...

Page 37: ...it D A output available in the PCI 69222 PCI 69223 card By switching the multiple front end multiplexers all A D input channels are connected to one ADC ADI AD7685 7686 or equivalent As for the D A fu...

Page 38: ...ction 2 3 In addition you should define and control the A D signal configurations including channels gains and signal types The A D acquisition is initiated by a trigger source and you must decide how...

Page 39: ...V 5V 2 5V 2V Least significant bit 305 2uV 152 6uV 76 3uV 61 03uV FSR 1LSB 9 999695V 4 999847V 2 499924V 1 999938V 7FFF Midscale 1LSB 305 2uV 152 6uV 76 3uV 61 03uV 0001 Midscale 0V 0V 0V 0V 0000 Mids...

Page 40: ...command is executed The software then polls the conversion status and reads back the A D data when it is available FSR 1LSB 1 249961V 0 999969V 0 499984V 0 249992V 7FFF Midscale 1LSB 38 14uV 30 51uV 1...

Page 41: ...trigger an A D conversion The conversion clock of PCI 69222 PCI 69223 may come from three different clock sources internal hardware timer general purpose input channel GPI 0 GPI 7 or SSI system synchr...

Page 42: ...n timing and the meaning of the four counters are illustrated in Figure 4 4 Timebase Clock Source In scan acquisition mode all A D conversions start on the output of counters which use Timebase as the...

Page 43: ...than the product of the data sampling interval and the NumChan_counter value The relation ship can be represented as SI_counter SI2_counter Num Chan_counter Specifying Channels Gains and Input Configu...

Page 44: ...d condition is detected on the selected trigger source For example a rising edge on the external digital trigger input These cards support post trigger with retrigger via software or an external digit...

Page 45: ...s two more scans are performed The process repeats until the specified amount of retrigger signals are detected The total acquired data length NumChan_counter PSC_counter Re trig_no For infinite retri...

Page 46: ...ndwidth The bus mastering controller controls the PCI bus when it becomes the master Bus mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to...

Page 47: ...ontinuous memory block to do the DMA transfer Therefore the PCI controller provides the function of scatter gather or chaining mode DMA to link the non continuous memory blocks into a linked list allo...

Page 48: ...In non chaining mode the maximum DMA data transfer size is 2M double words 8 MB However by using chaining mode scatter gather there is no limitation for the DMA data transfer size You may also link t...

Page 49: ...the relationship of straight binary coding between the digital codes and output voltages Software Update This method is suitable for applications that need to generate D A output controlled by user p...

Page 50: ...eneration D A conversions are updated automatically by the FPGA rather than by the application software Compare with the conventional software based waveform generation the precise hardware timing con...

Page 51: ...gure 4 12 Counter Name Width Description Note UI_counter 32 bit Update Interval Defines the update interval between each data output Update Interval UI_counter Timebase UC_counter 32 bit Update Counts...

Page 52: ...orm Generation DLY2_counter 32 bit Defines the delay time to separate consecutive waveform generation This is applicable only in Iterative Waveform Generation mode Delay Time DLY2_counter Clock Timeba...

Page 53: ...13 Post Trigger Generation Delay Trigger Generation Use delay trigger when you want to delay the waveform generation after the trigger signal The delay time is determined by DLY1_counter as illustrate...

Page 54: ...acceptable trigger signals Refer to Figure 4 15 In this example two waveforms are generated after the first trigger signal The card then waits for another trigger signal When the next trigger signal i...

Page 55: ...4 17 NOTE When IC_counter is disabled the waveform generation will not stop until a stop trigger is asserted An onboard data FIFO is used to buffer the waveform patterns for waveform generation If the...

Page 56: ...a 16 sample sine wave and set the UC_counter to 2 the generated waveform will be a 1 8 cycle sine wave for every waveform period and a complete sine wave will be generated for every 8 iterations If yo...

Page 57: ...pand the flexibility of iterative waveform generation DLY2_counter was implemented to separate consecutive waveform generations The DLY2_counter starts counting down right after a single waveform gene...

Page 58: ...and 5V TTL compliant TTL DI DO Programmable function I O can be used as static TTL compliant 8 CH digital input and 4 CH digital output You can read write these I O lines by software polling Its samp...

Page 59: ...ation Basic Timer Counter Functions Each timer counter has three inputs that can be controlled via hardware or software applications They are clock input GPTC_CLK gate input GPTC_GATE and up down cont...

Page 60: ...t operating following a software start signal that is set by the software The GPTC software reset initializes the status of the counter and reloads the initial value to the counter The operation remai...

Page 61: ...e application Figure 4 19 illustrates the operation where initial count 0 count up mode Figure 4 19 Mode 2 Operation Mode 3 Single Pulse width Measurement The counter counts the pulse width of the sig...

Page 62: ...oftware start The two programmable parameters can be specified in terms of periods of the GPTC_CLK input by the software application GPTC_GATE is use to enable disable counting When GPTC_GATE is inact...

Page 63: ...strates the generation of a single pulse with a pulse delay of two and a pulse width of four Figure 4 22 Mode 5 Operation Mode 6 Re triggered Single Pulse Generation This mode is similar to Mode 5 exc...

Page 64: ...is executed again Figure 4 24 illustrates the generation of two pulses with a pulse delay of four and a pulse width of three Figure 4 24 Mode 7 Operation Mode 8 Continuous Gated Pulse Generation This...

Page 65: ...time period via the known clock frequency The maximum counting width is 32 bit Figure 4 26 illustrates how the counter value decreases in Edge Separation Measurement mode Figure 4 26 Mode 9 Operation...

Page 66: ...rs it to the system memory via DMA The GPI is a 16 bit data and the sample clock source can be configured from an internal timer pacer internal analog conversion clock or external clock When using an...

Page 67: ...ock source can be configured from the onboard timer pacer internal analog conversion clock or external clock When using the internal timer pacer as update clock source the GPO supports data update rat...

Page 68: ...s position feedback The encoder sets are assigned in CN2 Encoder Isolation Input Module Figure 4 30 illustrates the encoder isolation phase A phase B and phase Z inputs module with 2500 Vrms protecti...

Page 69: ...When GPTC is set to CW CCW encoder mode and when the input EAx is connected to CW source signal and EBx is connected to CCW source signal pulses from EAx will cause the counter to counter up and spin...

Page 70: ...rature cycle and the increment and decrement of counter value in X1 encoder mode When phase A leads phase B the counter value increases on the first rising edge of CLK after phase A goes high When pha...

Page 71: ...l with phase A and B at a specific logic condition You must ensure that the logic level of phase Z is high during at least a portion of the phase you specify for reload when you use phase Z Otherwise...

Page 72: ...G2 ORG1 is used with phase Z With ORG enabled a high level on phase Z and ORG causes the counter to reload with a specified value in a specified phase of the quadrature cycle When you use ORG signal i...

Page 73: ...l Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the PCI 69222 PCI 69223 function I O You can set any DI line as...

Page 74: ...64 Operation Theory...

Page 75: ...values either from the original factory calibration or from a subsequently performed calibration Because of the fact that measurements and outputs errors may vary depending on time and temperature it...

Page 76: ...to the user configurable section of the EEPROM When auto calibration is completed you can save the new calibration constants to the user configurable banks in the EEPROM The date and the temperature w...

Page 77: ...original manufacturers warranty For products containing storage devices hard drives flash cards etc please back up your data before send ing them for repair JYTEK is not responsible for any loss of da...

Page 78: ...age environments i e high temperatures high humidity or volatile chemi cals Damage caused by leakage of battery fluid during or after change of batteries by customer user Damage from improper repair b...

Page 79: ...tact us should you require any service or assistance SHANGHAI JYTEK CO LTD Web Site http www jytek com Sales Service service jytek com Telephone No 86 21 50475899 Fax No 86 21 50475899 Mailing Address...

Page 80: ...70 Getting Service...

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