JVC SR-VS30E/EK, Service Manual

Page: 131 / 136

4-61 4-62
4.33 SYSTEM CONTROL BLOCK DIAGRAM (VHS)
(RESET)
SHTL(L)
OSC1(IN)
OSC2(OUT)
(10MHz)
(32KHz)
(SYSTEM CONTROL MICRO PROCESSOR)
VOLTAGE CONTROL)
(LOADING MOTOR
MAIN ( VHS SYSCON, CONNECTION)
TO
OSD
TO
DV MAIN (DV MSD)
AL5V
S3002
S.CASS
65
X1
Q3002
Q3003
CLOCK
SYSTEM
64
67
69
MAIN
CLOCK
X3002
TIMER
53
52
51
41
S.CLK
X2
TXD/KBUS_OUT
END
START
15
14
SENSOR
SENSOR
X3001
S.CLK
TO
VIDEO/AUDIO
TO
TUNER
IC3003
49
50
6
5
61
60
76
75
SDA
SCL
IC3001
28
3 0
CN3003
MDA
8
101
CAPPWM
CFG
107
108
DPG
DFG
55
54
102
PHOTO
PC3002
PC3001 SENSOR PHOTO
35
LMC1
37
LMC3
LMC2
36
26
27
LSB
25
LSA
LSC
TP4001
CTL.P
SENSOR
AGE VOL T
CONTROL
DRIVE
Q3001
IC3004
3
2
CN3001
4
5
3
D.PG
D.FG
4
3
5
9
LMC1
1
Vref
LMC2
7
LDM2
2
LDM1
4
2
CN3002
1
LDM1
LDM2
1
LSB
CN3004
3
LSA
2
LSC
AR Y ROT
ENCODER
MOTOR
6
CAP
5 5
M
DRUM MOTOR
M
M
CON1
LOADING
1
3
98
100
V.FF
66
RES
TP3905
3
2
RESET
D3004
1
71
MODE
97
94
JSA/STLA
FWE
62
95
JSB/STLB
Vcc
TP3904
IC3002
CN2001
7
6
D.FF
C.SYNC/VREF
20
CN3011
19
TP3903
AL5.8V
1
2
HEAD
HEAD
A/C
A/C
CTL
8 5 JOG
JOG/SHUTTLE
UNIT
FW7004
CN1
1 2
6
CTLAMPOUT
CTL HEAD(-)
CTL HEAD(+)
CTL(-)
CTL(+)
(SERIAL MEMORY)
TO
TERMINAL
I2C CLK2
I2C DATA2
I2C DATA2
I2C CLK2
CAP REV(L)
CAP CTL V
CAP FG
DRUM CTL V
SHUTTLE(L)
JSA/SHUTTLE A
JSB/SHUTTLE B
S.DATA FRSYS
I2C DATA A/V
I2C CLK A/V
TU DATA
TU CLK
SP FG
S.DATA TOSYS
REC SAFETY
END SENSOR
START SENSOR
I2C DATA A/V
I2C CLK A/V
TU DATA
TU CLK
I2C DATA2
I2C CLK2
TU FG
CAP REV (L)
S.DATA FRSYS
DRUMPWM
C. SYNC
17
1
2
4
FW7003
20
19
17
1
2
4
2 8 SW/DISPLAY(FRONT)
CN7001
Note : For the waveforms in this block diagram, refer to page 4-55.
S3001
REC_SAFETY
96
S_CASS(H)
RXD/KBUS_IN
DIAL_OFF[H]/KBUS_REQ
RXD
TXD
DV_HOUSING_SW/HDD_RESET
DIAL_OFF(L)
DV_H.SW
TP3911
TP3910
WF1
WF2
WF3
WF4
WF5
WF6
46
47
56
CN3014
2
1
4
3
Q7501 SW
CN1503
Q3010,Q3011
SW
AL5V
57
CN7507
7
6
I2C CLK2
I2C DATA2
4
3
2
4
3
2
S.CLK
S.DATA TOSYS
S.DATA FRSYS
TO
OSD
(AUDIO CTL)
7
9
CLK
IC3651
2
3
5
6
8
FULL_E_ON(L)
N.REC(L)
DATA2
INSEL_A
FULL_E_ON(L)
N.REC(L)
INSEL_B
OUTSEL_B
OUTSEL_A
INSEL_A
INSEL_B
OUTSEL_B
OUTSEL_A
10
(VIDEO/TUNER/REG CTL)
14
13
CLK
IC3601
2
3
15
10
8
SP_CONV(H)
BIL_SEL
DATA2
P.SAVE(L)
SP_CONV(H)
BIL_SEL
P.CTL(H)
D_OUT(L)
VHS(H)
D_OUT(L)
VHS(H)
5
6
FLY_REC(L)
FLY_REC(L)
FAN_CTL(H)
P.SAVE(L)
P.CTL(H)
CN7509
2
1
3
OSD_P.CTL(L)
EXP1_DATA
33
EXP2_DATA
96
EXP_CLK
79
FAN_CTL(H)/MESECAM(H)
93
13
Sin
15
SCLK
Sout
14
IC7001
(FLD CTL)
DI7001
9
11
10
AN2
AN0
AN1
OPE
DATA
TO
REG
CN5321
TO
AUDIO I/O
TO
VIDEO I/O
TO
VIDEO/AUDIO
FW7002
1
3
2 7 POWER SW
1
3
FW7001