JVC RX-7520VBK, Service Manual

Page: 11 / 61

RX-7520VBK
1-11
No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Symbol
ICKS
ADIF
CAD1
CAD0
LOUT3
ROUT3
LOUT2
ROUT2
LOUT1
ROUT1
LIN-
LIN+
RIN-
RIN+
VREFL
OVF
VCOM
VREFH
AVDD
AVSS
XTI
XTO
P1S
CS
CSN
DIF1
SCL/CCLK
LOOP0
SAD/CDTI
CDTD
Connect to GND
No internal bonding.
Analog Input Format Select Pin, Digital Power Supply
"H" : Full-differential input, "L" : Single-ended input
Chip Address 1 Pin, Connect to GND
Chip Address 0 Pin, Connect to GND
DAC3 Lch Analog Output Pin
DAC3 Rch Analog Output Pin
DAC2 Lch Analog Output Pin
DAC2 Rch Analog Output Pin
DAC1 Lch Analog Output Pin
DAC1 Rch Analog Output Pin
Lch Analog Negative Input Pin
Lch Analog Positive Input Pin
Rch Analog Negative Input Pin
Rch Analog Positive Input Pin
Zero Input Detect 2 Pin (Note 2), Non Connect
When the input data of the group 1 follow total 8192LRCK cycles with "0"
input data, this pin goes to "H".
Analog Input Overflow Detect Pin (Note 3)
This pin goes to "H" if the analog input of Lch or Rch is overflows.
Common Voltage Output Pin,AVDD/2
Large external capacitor around 2.2uF is used to reduce power-supply noise.
Positive Voltage Reference Input Pin,AVDD
Analog Power Supply Pin,4.5V~5.5V
Analog Ground Pin,0V
Zero Input Detect 1 Pin (Note 2), Non connect
When the input data of the group 1 follow total 8192 LRCK cycles with "0"
input data, this pin goes to "H".
Master Clock Input Pin
Parallel / Serial Select Pin
"L" : Serial control mode, "H" : Parallel control mode
Audio Data Interface Format 0 Pin in parallel mode
Chip select pin in 3-wire serial control mode
This pin should be connected to DVDD at I2C bus control mode
Audio Data Interface Format 1 Pin in parallel mode
Control Data Clock Pin in serial control mode
I2C = "L" : CCLK(3-wire Serial), I2C = "H" : SCL(I2CBus)
Loopback Mode 0 Pin in parallel control mode
Enables digital loop-back from ADC to 3 DACs.
Control Data Input Pin in serial control mode
I2C = "L" : CDTI(3-wire Serial), I2C = "H" : SDA(I2CBus)
Loopback Mode 1 Pin (Note 1)
Enable all 3 DAC channels to be input from SDTII.
Function
AK4527
I/O
-
-
-
-
O
O
O
O
O
O
I
I
I
I
-
O
O
-
-
-
-
I
-
I
I
I
I
I
I/O
I
Pin function (2/2)
Notes : 1. SDOS, SMUTE, DFS, and LOOP1 pins are ORed with register data if P/S = "L".
2. The group 1 and 2 can be selected by DZFM2-0 bit if P/S = "L" and DZFME = "L".
3. This pin becomes OVF pin if OVFE bit is set to "1" at serial control mode.
4. All input pins should not be left floating.