RX-5030VBK
1-20 (No.22025)
4.12 LP61L1024S-12-X (IC641) : SRAM
• Pin layout
• Block diagram
• Pin function
4.13 TC74HC08AF-X(IC611) : AND gate
• Block diagram
• Truth table
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
SYMBOL
DESCRIPTION
A0 - A16
Address Input
I/O1 - I/O8
Data Input/Output
CS1, CS2
Chip Select Inputs
WE
Write Enable Input
OE
Output Enable Input
VDD
Power Supply
Vss
Ground
NC
No Connection
DECODER
CORE
ARRAY
CONTROL
DATA I/O
V
DD
Vss
CS2
CS1
OE
WE
A0
A16
I/O1
I/O8
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
4B
4A
4Y
3B
3A
3Y
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
A
B
Y
L
L
L
L
H
L
H
L
L
H
H
H