1-32 (No.49858)
4.16 UPD784215AGC184 (IC701) : CPU
• Pin layout
• Pin function
75
51
1
25
50
26
76
100
Pin No.
Symbol
I/O
Function
1
SW2
I
CD mechanism detect switch
2
SW3
I
CD mechanism detect switch
3
SW4
I
CD mechanism detect switch
4
REST
I
Reset signal input terminal from CD mechanism
5
LM0
O
Loading motor control signal input terminal
6
LM1
O
Loading motor control signal input terminal
7
NC
-
Not use
8
ANTCRTL
O
Antenna control signal output
9
VDD
-
Power supply terminal
10
X2
O
Connect to system main clock X'tal osc
11
X1
I
Connect to system main clock X'tal osc
12
VSS
-
Connect to ground
13
XT2
O
Connect to system sub clock X'tal osc
14
XT1
I
Connect to system sub clock X'tal osc
15
RESET
I
System reset signal input terminal
16
SW1
I
CD mechanism detect switch
17
BUS-INT
I
J-BUS signal cut in input terminal
18
PS2
I
Power save 2
19
NC
-
Not use
20
NC
-
Not use
21
NC
-
Not use
Remote control signal input terminal
Power supply terminal
Power supply terminal
Volume control signal output
Volume control signal output
Key control 0 input terminal
Key control 1 input terminal
Key control 2 input terminal
30
LEVEL
I
Level meter signal input terminal
31
SQ
I
S. quality level input terminal
32
SM
I
S. meter level input terminal
33
AVSS
-
Connect to ground
34
NC
-
Not use
35
NC
-
Not use
36
AVREF
-
Power supply terminal
37
BUSSI
I/O
J-BUS data I/O terminal
38
BUSSO
O
J-BUS data out put terminal
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9
2
8
9
4
2
9
8
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9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
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