MX-K50
1-28
2. Block diagram
5L9290 (IC201) : Digital signal processor for CDP
1. Pin layout
DPLL
CLV
Servo
LOCK
SMEF
SMDP
SMDS
WDCK
EFMI
VCO1LF
Timing
Generator
Micom
Interface
WFCK
RFCK
C4M
XIN
ISTAT
MLT
MDAT
MCK
MUTE
Subcode
Out
EFM
Demodulator
ECC
16K
SRAM
Address
Generator
SQCK
SBCK
SOS1
SQDT
SBDT
Interpolator
I/O
Interface
JITB
LPF
PWM
SADTO
LRCKO
BCKO
LCHOUT
RCHOUT
VHALF
VREF
1-bit
DAC
Digital
Out
Digital
Filter
C2PO
DATX
SADTI
LRCKI
BCKI
S5L9290X
DSP+DAC
48-LQFP-0707
VSSA_PLL
VCO1LF
VSSD_PLL
VDDD_PLL
XIN
XOUT
EFMI
LOCK
SMEF
C2PO
JITB
DATX
VDDD3-5V
VDDD2-3V
SBCK
SQDT
SMON
TESTV
SMDS
WDCK
MUTE
BCKI
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
VDDD1_5V
VSSD1_5V
LKFS
LKFS
RESETB
MLT
MDAT
MCK
ISTAT
S0S1
SQCK
VSSD2-3V
SADTO
LRCKO
BCKO
LRCKI
SADTI
VSSD_DAC
VDDD_DAC
RCHOUT
VSSA_DAC
VREF
VHALF
VDDA_DAC
LRHOUT
VDDA_PLL
Description of major ICs