JHCTech FEBC-3150, User Manual

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User’s Manual
31
Debug Command Line
- O A16 05
- O A15 32 // 5 sec // 3A 5 minutes
Watchdog Timer Function
Watch dog timer is provided for system controlling. If time
‐
out can trigger one signal to
high/low level/pulse, the signal is depend on register setting.
The time unit has two ways from 1sec or 60sec. In pulse mode, there are four pulse
widths can be selected (1ms/25ms/125ms/5sec). Others, please refer the device register
description as below.
Watchdog Timer Configuration Register 1
‐
base a05h
Bit Name R/W Default Description
7 Reserved R 0
Reserved
6 WDTMOUT_STS R/W 0
If watchdog timeout event occurs, this bit will be set to
1. Write a 1 to this bit will clear it to 0.
5 WD_EN R/W 0
If this bit is set to 1,the counting of watchdog time is
enabled.
4 WD_PULSE R/W 0
Select output mode (0:level,1:pulse)of RSTOUT# by
setting this bit.
3 WD_UNIT R/W 0
Select time unit (0:1sec, 1:60sec) of watchdog timer by
setting this bit.
2 WD_HACTIVE R/W 0
Select output polarity of RETOUT# (1:high active,
0:low active) by setting the bit.
1
‐
0
WD_PSWIDTH R/W 0
Select output pulse width of RSTOUT#
0:1 ms 1:25 ms 2:125 ms 3:5 sec
Table 5.3
Watchdog Timer Configuration Register 2
‐
base a06h
Bit Name R/W Default Description
7
‐
0 WD_TIME R/W 0 Time of watchdog timer
Table 5.4