26
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast
gives faster performance; and
Slow
gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 7T, 6T and 5T.
RAS to CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T and 3T.
CAS Latency Setting
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: Auto (Default) 2T and 3T.
3-6-2 AGP Function Settings
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
AGP Function Settings
Item Help
AGP Transfer Mode Auto
AGP Fast Write Disabled
AGP Aperture Size 64MB
AGP Aperture Write Combining Enabled
AGP Driving Control Auto
AGP Driving Value 88
System Share Memory Size 16MB
Menu Level >>
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
3-7 Integrated Peripherals
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Integrated Peripherals
Item Help
> OnChip IDE Function Press Enter
> OnChip Device Function Press Enter
> Onboard SuperIO Function Press Enter
Power Loss Function Always Off
Init Display First PCI Slot
Menu Level >
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
OnChip IDE Function
Please refer to section 3-7-1
