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CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Advanced Chipset Features
Item Help
> DRAM Timing Settings Press Enter
> AGP Function Settings Press Enter
Prefetch Caching Disabled
Memory Hole at 15M-16M Disabled
Menu Level >
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
DRAM Timing Settings
Please refer to section 3-6-1
AGP Function Settings
This option determines the effective size of the graphics aperture used in the particular PAC
configuration. The AGP aperture is memory-mapped, while graphics data structure can reside
in a graphics aperture. The aperture range should be programmed as not cacheable in the
processor cache, accesses with the aperture range are forwarded to the main memory, then
PAC will translate the original issued address via a translation table that is maintained on the
main memory. The option allows the selection of an aperture size of 32MB, 64MB.
Please refer to section 3-6-2
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
3-6-1 DRAM Timing Setting
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
DRAM Timing Setting
Item Help
Auto Configuration Standard
RAS Active Time 7T
RAS Precharge Time 2T
RAS to CAS Delay 2T
Write Recovery Time 2T
CAS Latency Setting 2.5T
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
RAS Active Time
Select the number of SCLKs for an access cycle. The settings are: Auto (Default), 6T, 7T, 5T,
4T.
