23
3-6-1 DRAM Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
DRAM Timing Settings
Item Help
System Performance
Standard
RAS Active Time
7T
RAS Precharge Time
4T
RAS to CAS Delay
3T
DRAM CAS Latency
2.5
Bank Interleave
Enabled
DRAM Command Rate
2T Command
DRAM Burst Length
4
Write Recovery Time
3T
Write to Read Command Delay
2T
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
RAS Active Time
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T and 3T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast
gives faster performance; and
Slow
gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
3-6-2 AGP Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
AGP Timing Settings
Item Help
AGP Aperture Size
64M
AGP Transfer Mode
4X
AGP Driving Control
Auto
AGP Driving Value
9A
AGP Fast Write Disabled
AGP Master 1 WS Write
Enabled
AGP Master 1 WS Read
Enabled
CPU to AGP Post Write
Enabled
AGP Delay Transaction
Enabled
AGP 3.0 Calibration Cycle Enabled
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Note: Change these settings only if you are familiar with the chipset.
