32
During Enabled, A deferrable CPU cycle will only be Deferred after it has been in a Snoop
Stall for 31 clocks and another ADS# has arrived. During Disabled, A deferrable CPU cycle
will be Deferred immediately after the GMCH receives another ADS#.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
On-Chip Video Window Size
This option enabled/disabled the on-chip video windows size for VGA driver use. The
settings are: enabled, Disabled.
AGP Graphics Aperture Size
This option determines the effective size of the graphics aperture used in the particular PAC
configuration. The AGP aperture is memory-mapped, while graphics data structure can reside
in a graphics aperture. The aperture range should be programmed as not cacheable in the
processor cache, accesses with the aperture range are forwarded to the main memory, then
PAC will translate the original issued address via a translation table that is maintained on the
main memory. The option allows the selection of an aperture size of 32MB, 64MB.
3-6-1 SDRAM Timing Setting
CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
SDRAM Timing Setting
Item Help
SDRAM CAS Latency Time 3
SDRAM Cycle Time Tras/Trc 6/8
SDRAM RAS-to-CAS Delay 3
SDRAM RAS Precharge Time 3
DRAM CTL Buffer strengths Normal
DRAM MD Buffer strengths Normal
Menu Level >>
When set to “Auto”,
BIOS will program this
Timing mainly by the
SPD method. SPD means
“Serial Presence
Detect”, which enables
the BIOS to access
the manufacturer
settings stored in
DRAM module.
↑↓→←
Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
SDRAM CAS Latency Time
