6 - 26
emPC-CXR
(
Hardware Manual
)
•
FPGA expansion subsystem
©
Janz Tec AG
Rev. V1.2
I2C_CONTROL
BAR4 +
0x1c (32bit, rw)
31..10
9
8
7..2
1
0
reserved
SCL
SDA
SDA
I
2
C bidirectional data line.
Writing 0 sets the data line to low potential.
Writing 1 tristates the data line. An external pull-up resistor (1kOhm)
raises the line to high potential. This must be done before reading data.
SCL
I
2
C “bidirectional” clock line.
Writing 0 sets the clock line to low potential.
Writing 1 tristates the clock line. An external pull-up resistor (1kOhm)
raises the line to high potential. This must be done before reading clock
status.
Reserved
Reserved bit positions must be written as zero.
6.2
CAN Interface
6.2.1
CAN address space
The CAN controllers are mapped into memory address space
Address Offset
accesses:
BAR2 + 0x000..0x0ff
CAN controller 0 registers (SJA1000)
BAR2 + 0x100..0x102
CAN controller 0 control
BAR2 + 0x200..0x2ff
CAN controller 1 registers (SJA1000)
BAR2 + 0x300..0x302
CAN controller 1 control
Refer to SJA1000 manual for description of registers and operation.
6.2.2
CAN termination and LEDs
Besides the registers of the SJA1000 (which are defined in the SJA1000 Manual), there are two
additional registers which control the line termination and the front panel LEDs. These registers are
unique for each channel.
CAN_TERM0,1
BAR2 +
0x100, 0x300 (byte, rw)
7
6
5
4
3
2
1
0
reserved
TERM
RESET:
-
0
TERM
Set to zero to disable the line-termination, Set to one to enable the
termination resistor.
Reserved
Reserved positions should not be changed. You should use read-modify-
write operation to change this register.
CAN_LED0,1
BAR2 +
0x102, 0x302 (byte, wo)
7
6
5
4
3
2
1
0
reserved
LEDG
LEDR
RESET:
-
0
0
LEDR
Write 1 to turn red LED on, write 0 to disable.
LEDG
Write 1 to turn green LED on, write 0 to disable.
Reserved
Reserved positions should be written as zero for compatibility with future
products.
