CV-M71A
-20-
Important notes on using this mode
•
External sync system should follow the camera scanning system.
•
To avoid < 1 LVAL jitter if LS=0, ext. HD/Trigger phase relations as shown in Figure 19 on page 14.
•
Trigger pulse width: >2 LVAL to <120 frames in HD sync. accumulation.
•
Trigger pulse width: >2 LVAL to <3 frames in HD a-sync. accumulation.
•
If LS=0, the minimum trigger interval >(1 VD + 4 H).
•
If LS=1, the minimum trigger interval >(exposure time + 1 VD + 3 H).
•
PWC together with Smearless can only work in HD sync. accumulation (LS=0).
FIGURE 25.Pulse width control. HD async. accumulation
6.4.5 (a) Sensor Gate Control
This mode is for applications with strobe flash illuminations or long time accumulations up to several frames. In
this mode the camera runs continuously. The external Sensor Gate control signal will disable the internal XSG
pulse so the accumulation continues during the next frame. The resulting video is read out after the first VD (or
SG), following the trailing edge of the Sensor Gate Control signal.
Other functions and settings
Input
Ext. trigger
6-pin Hirose or 12-pin Hirose
Ext. HD in
D-sub p-pin or 12-pin connector
SW302.1 (If used)
T1: Exposure start delay
Sync. Accum
4-30
μ
s
Async. Accum
4
μ
s
