ADwin-light-16
, manual version 2.2, December 2004
37
DIO1 Add-On
ADwin
Global mask
With the global mask a message object is used for receiving messages with
different identifiers
(ID). The following example shows the assignment of the
message IDs 1...4 to the message object IDs 1...4, when all bits of the global
mask are set, except the two least-significant bits (if you have an 11-bit identi-
fier it is
11111111100b
).
In this example the comparison of bit 2 is responsible for the assignment of the
messages, because the bits 3...10 of the compared identifiers are identical (=
0) and the bits 0 and 1 are not compared, because they are set to zero in the
global mask (= not relevant).
Setting the bus frequency
The
CAN bus frequency
depends on the configuration of the controller.
The initialization routine configures the controller automatically so that the
CAN bus frequency is 1 MHz. If the CAN bus is to operate with another fre-
quency, the values in the "Bit Timing Register 0 (BTR0, address 3Fh) and in the
"Bit Timing Register 1" (BTR1, address 4Fh) have to be changed. Just use the
instruction
SET_CAN_BAUDRATE
for setting a large quantity of bus frequen-
cies.
Special cases
In some special cases it may be better to select configurations other than those
set with the instruction mentioned above. For this purpose specified registers
have to be set with the instruction
POKE
. The structure of the register is
described below.
The following table shows the admitted values and the meaning of the individ-
ual ranges:
The default setting of the ranges SJW and SPL is 0 and should only be
changed if necessary. Select the sample point (specified by TSEG1 and
TSEG2) in such a way that it is between 50% and 80% of the total bit length.
The CAN bus frequency is calculated as follows:
Message ID
ID of the message object
1
…001b
2
…010b
3
…011b
4
…100b
1 (
…001b
)
x
x
x
0
2 (
…010b
)
x
x
x
0
3 (
…011b
)
x
x
x
0
4 (
…100b
)
0
0
0
x
x: Message is admitted
0: Message is not admitted
Bit Timing Register 0
(BTR0)
Bit Timing Register 1
(BTR1)
Bits
7…6
5…0
7
6…4
3…0
Sub-Reg.
SJW
BRP
SPL
TSEG2 TSEG1
Range
Admitted
values
Meaning
SJW
0 … 3
Max. pulse elongation during bus synchronization
BRP
0 … 63
Pre-scaler
SPL
0 … 1
Sampling mode
TSEG1
2 … 15
Time segments before sampling
TSEG2
1 … 7
Time segments after sampling
