IXYS zilog Z51F3220 Manual Download

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Z51F3220

Product Specification

PS029902-0212

P R E L I M I N A R Y

132

Figure 11.23 16-Bit Timer/Counter 2 Example

T2CNTH/L

Value

Timer 2

(T2IFR)

Interrupt

TIME

n-2

n-1

Interrupt Period

= P

x (n+1)

Count Pulse Period

Up-count

Match with T2ADRH/L

Occur

Interrupt

Occur

Interrupt

Occur

Interrupt

Summary of Contents for zilog Z51F3220

Page 2: ...ure to perform can be reason ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Document Disclaimer 2012 Zilog Inc All rights reserved Inf...

Page 3: ...ce in this document s revision history reflects a change from its previous edi tion For more details refer to the corresponding page s or appropriate links furnished in the table below Date Revision L...

Page 4: ...tics 31 7 7 Internal Watch Dog Timer RC Oscillator Characteristics 31 7 8 LCD Voltage Characteristics 32 7 9 DC Characteristics 33 7 10 AC Characteristics 35 7 11 SPI0 1 2 Characteristics 36 7 12 UART...

Page 5: ...9 11 1 Clock Generator 99 11 2 Basic Interval Timer 102 11 3 Watch Dog Timer 105 11 4 Watch Timer 108 11 5 Timer 0 111 11 6 Timer 1 120 11 7 Timer 2 130 11 8 Timer 3 4 141 11 9 Buzzer Driver 170 11 10...

Page 6: ...Z51F3220 Product Specification PS029902 0212 P R E L I M I N A R Y 3 15 1 Overview 293 16 Configure Option 304 16 1 Configure Option Control 304 17 APPENDIX 305...

Page 7: ...3 Figure 7 13 Clock Timing Measurement at SXIN 43 Figure 7 14 Operating Voltage Range 44 Figure 7 15 Recommended Circuit and Layout 45 Figure 7 16 RUN IDD1 Current 46 Figure 7 17 IDLE IDD2 Current 46...

Page 8: ...ration for Timer 2 134 Figure 11 26 Express Timer Overflow in Capture Mode 134 Figure 11 27 16 Bit PPG Mode for Timer 2 135 Figure 11 28 16 Bit PPG Mode Timming chart for Timer 2 136 Figure 11 29 16 B...

Page 9: ...er Receiver Mode USI0 207 Figure 11 75 Formats and States in the Slave Transmitter Mode USI0 209 Figure 11 76 Formats and States in the Slave Receiver Mode USI0 211 Figure 11 77 USI0 I2C Block Diagram...

Page 10: ...ng Time 278 Figure 13 4 Internal RESET Release Timing On Power Up 278 Figure 13 5 Configuration Timing when Power on 279 Figure 13 6 Boot Process WaveForm 279 Figure 13 7 Timing Diagram after RESET 28...

Page 11: ...nce 40 Table 7 17 Main Clock Oscillator Characteristics 41 Table 7 18 Sub Clock Oscillator Characteristics 42 Table 7 19 Main Oscillation Stabilization Characteristics 43 Table 7 20 Sub Oscillation St...

Page 12: ...Register Map 213 Table 11 22 Equations for Calculating USI1 Baud Rate Register Setting 225 Table 11 23 CPOL1 Functionality 233 Table 11 24 USI1 Register Map 250 Table 11 25 Examples of USI0BD and USI1...

Page 13: ...is provides the following features 32k bytes of Flash 256 bytes of IRAM 768 bytes of XRAM general purpose I O basic interval timer watchdog timer 8 16 bit timer counter 16 bit PPG output 8 bit PWM out...

Page 14: ...resistor bias 1 2 1 3 1 4 1 5 1 6 and 1 8 duty selectable Resistor Bias and 16 step contrast control Power On Reset Reset release level 1 4V Low Voltage Reset 14 level detect 1 60V 2 00V 2 10V 2 20V 2...

Page 15: ...9902 0212 P R E L I M I N A R Y 12 1 3 Ordering Information Table 1 1 Ordering Information of Z51F3220 Device Name ROM Size IRAM Size XRAM Size Package Z51F3220FNX 32k bytes Flash 256 bytes 768 bytes...

Page 16: ...emory F General Purpose Flash Device Family Z51 Z8051 8 Bit Core MCU 1 4 Development Tools 1 4 1 Compiler We do not provide the compiler Please contact the third parties The core of Z51F3220 is Mentor...

Page 17: ...I M I N A R Y 14 If you want to see more details please refer to OCD debugger manual You can download debugger S W and manual from our web site Connection SCLK Z51F3220 P01 port SDATA Z51F3220 P00 por...

Page 18: ...cause OCD debugging supports ISP In System Programming It does not require additional H W except developer s target system Gang programmer It programs 8 MCU devices at once So it is mainly used in mas...

Page 19: ...LCD Driver Controller COM0 COM1 P37 P36 COM2 COM7 SEG0 SEG5 P35 P30 SEG6 SEG29 P27 P03 VLC0 VLC3 P43 P40 P5 Port P50 XOUT Low Voltage Indicator USI1 UART1 SPI1 I2C1 On Chip Debug DSDA DSCL INT RC OSC...

Page 20: ...17 SEG21 AN6 EINT6 SS2 P07 SEG22 AN5 EINT5 PWM4CB P15 SEG19 AN8 MISO2 P16 SEG20 AN7 EINT7 SCK2 P13 SEG17 AN10 EC1 BUZO P14 SEG18 AN9 MOSI2 P06 SEG23 AN4 EINT4 PWM4CA P25 SE G8 P24 SE G9 P23 SE G10 P22...

Page 21: ...RXD0 SCL0 MISO0 P41 VLC2 TXD0 SDA0 MOSI0 P32 COM5 SEG3 P31 COM6 SEG4 P30 COM7 SEG5 P27 SEG6 P42 VLC 1 SCK0 P33 COM4 SEG2 P05 SEG24 AN3 EINT3 PWM4BB P04 SEG25 AN2 EINT2 PWM4BA P13 SEG17 AN10 EC1 BUZO...

Page 22: ...Z51F3220 Product Specification PS029902 0212 P R E L I M I N A R Y 19 4 Package Diagram Figure 4 1 44 Pin MQFP Package...

Page 23: ...Z51F3220 Product Specification PS029902 0212 P R E L I M I N A R Y 20 Figure 4 2 32 Pin SOP Package...

Page 24: ...N11 EINT11 T1O PWM1O P13 SEG17 AN10 EC1 BUZO P14 SEG18 AN9 MOSI2 P15 SEG19 AN8 MISO2 P16 SEG20 AN7 EINT7 SCK2 P17 SEG21 AN6 EINT6 SS2 P20 I O Port 2 is a bit programmable I O port which can be configu...

Page 25: ...EINT11 I O External interrupt input and Timer 1 capture input Input P12 SEG16 AN11 T1O PWM1O EINT12 I O External interrupt input and Timer 2 capture input Input P11 SEG15 AN12 T2O PWM2O T0O I O Timer...

Page 26: ...G11 SS2 I O SPI 2 slave select input Input P17 SEG21 AN6 EINT6 TXD0 I O UART 0 data output Input P41 VLC2 SDA0 MOSI0 TXD1 I O UART 1 data output Input P20 SEG13 AN14 SDA1 MOSI1 RXD0 I O UART 0 data in...

Page 27: ...COM4 COM7 P33 P30 SEG2 SEG5 SEG0 SEG1 I O LCD segment signal outputs Input P35 P34 COM2 COM3 SEG2 SEG5 P33 P30 COM4 COM7 SEG6 SEG10 P27 P23 SEG11 P22 SS1 SEG12 P21 SCK1 AN15 SEG13 P20 AN14 TXD1 SDA1...

Page 28: ...ator pins Input P53 T0O PWM0O SXOUT P54 EINT10 VDD VSS Power input pins NOTES 1 The P14 P17 P23 P25 P34 P37 and P43 are not in the 32 pin package 2 The P55 RESETB pin is configured as one of the P55 a...

Page 29: ...ER VDD VDD PAD VDD OPEN DRAIN REGISTER DATA REGISTER DIRECTION REGISTER MUX 0 1 MUX 1 0 CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or SUB FUNC DATA INPUT SUB FUNC DIREC...

Page 30: ...ER MUX 0 1 MUX 1 0 INTERRUPT ENABLE EXTERNAL INTERRUPT Q D CP r VDD FLAG CLEAR POLARITY REG MUX 1 0 DEBOUNCE ENABLE Q D CP r DEBOUNCE CLK CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT...

Page 31: ...C NOTE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at any other conditions...

Page 32: ...VAN VSS AVREF V Analog Reference Voltage AVREF 1 8 VDD Analog Input Leakage Current IAN AVREF 5 12V 2 A ADC Operating Current IADC Enable VDD 5 12V 1 2 mA Disable 0 1 A NOTES 1 Zero offset error is t...

Page 33: ...ction Level VLVR VLVI The LVR can select all levels but LVI can select other levels except 1 60V 1 60 1 75 V 1 85 2 00 2 15 1 95 2 10 2 25 2 05 2 20 2 35 2 17 2 32 2 47 2 29 2 44 2 59 2 39 2 59 2 79 2...

Page 34: ...16 MHz Tolerance TA 25 C 0 5 TA 0 C to 70 C 1 TA 20 C to 80 C 2 TA 40 C to 85 C 3 Clock Duty Ratio TOD 40 50 60 Stabilization Time THFS 100 S IRC Current IIRC Enable 0 2 mA Disable 0 1 A 7 7 Internal...

Page 35: ...03H VDDx16 28 LCDCCR 04H VDDx16 27 LCDCCR 05H VDDx16 26 LCDCCR 06H VDDx16 25 LCDCCR 07H VDDx16 24 LCDCCR 08H VDDx16 23 LCDCCR 09H VDDx16 22 LCDCCR 0AH VDDx16 21 LCDCCR 0BH VDDx16 20 LCDCCR 0CH VDDx16...

Page 36: ...cept VIL1 0 3VDD V Output High Voltage VOH VDD 4 5V IOH 2mA All output ports VDD 1 0 V Output Low Voltage VOL1 VDD 4 5V IOL 10mA All output ports except VOL2 1 0 VOL2 VDD 4 5V IOL 15mA P1 1 0 V Input...

Page 37: ...fXIN 10MHz VDD 3V 10 1 3 2 6 fIRC 16MHz VDD 5V 10 1 5 3 0 IDD3 fXIN 32 768kHz VDD 3V 10 TA 25 C Sub RUN 50 0 80 0 A IDD4 Sub IDLE 8 0 16 0 A IDD5 STOP VDD 5V 10 TA 25 C 0 5 3 0 A NOTES 1 Where the fX...

Page 38: ...Unit RESETB input low width tRSL Input VDD 5V 10 S Interrupt input high low width tINTH tINTL All interrupt VDD 5V 200 nS External Counter Input High Low Pulse Width tECWH tECWL ECn VDD 5 V n 0 1 3 20...

Page 39: ...ce 200 Output Clock High Low Pulse Width tSCKH tSCKL Internal SCK source 70 Input Clock High Low Pulse Width External SCK source 70 First Output Clock Delay Time tFOD Internal External SCK source 100...

Page 40: ...edge tS1 590 tCPU x 13 nS Clock rising edge to input data valid tS2 590 nS Output data hold after clock rising edge tH1 tCPU 50 tCPU nS Input data hold after clock rising edge tH2 0 nS Serial port cl...

Page 41: ...Pulse Width tSCLH 4 0 0 6 S Clock Low Pulse Width tSCLL 4 7 1 3 Bus Free Time tBF 4 7 1 3 Start Condition Setup Time tSTSU 4 7 0 6 Start Condition Hold Time tSTHD 4 0 0 6 Stop Condition Setup Time tSP...

Page 42: ...de Watchdog Timer Active VDD NOTE tWAIT is the same as the selected bit overflow of BIT X 1 BIT Clock INT Request Execution of STOP Instruction Data Retention Stop Mode Normal Operating Mode 0 8VDD tW...

Page 43: ...d Lock Time tFHL 2 5 2 7 Page Buffer Reset Time tFBR 5 S Flash Programming Frequency fPGM 0 4 MHz Endurance of Write Erase NFWE 100 000 Times NOTE During a flash operation SCLK 1 0 of SCCR must be set...

Page 44: ...TYP MAX Unit Crystal Main oscillation frequency 1 8V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 10 0 3 0V 5 5V 0 4 12 0 Ceramic Oscillator Main oscillation frequency 1 8V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 10 0 3 0V...

Page 45: ...lock Oscillator Characteristics TA 40 C 85 C VDD 1 8V 5 5V Oscillator Parameter Condition MIN TYP MAX Unit Crystal Sub oscillation frequency 1 8V 5 5V 32 32 768 38 kHz External Clock SXIN input freque...

Page 46: ...is equal to the minimum oscillator voltage range 60 mS Ceramic 10 mS External Clock fXIN 0 4 to 12MHz XIN input high and low width tXH tXL 42 1250 nS tXH tXL XIN 0 2VDD 0 8VDD 1 fXIN Figure 7 12 Clock...

Page 47: ...29902 0212 P R E L I M I N A R Y 44 7 21 Operating Voltage Range 1 8 0 4MHz 3 0 5 5 12 0MHz fXIN 0 4 to 12MHz Supply voltage V 4 2MHz 1 8 5 5 32 768KHz Supply voltage V fSUB 32 to 38KHz 10 0MHz 2 7 Fi...

Page 48: ...citor is alternatively for noise immunity X tal SXOUT SXIN 32 768kHz The main and sub crystal should be as close by the MCU as possible 0 1uF VDD VCC The MCU power line VDD and VSS should be separated...

Page 49: ...guaranteed to operate properly only within the specified range The data presented in this section is a statistical summary of data collected on units from different lots over a period of time Typical...

Page 50: ...M I N A R Y 47 Figure 7 18 SUB RUN IDD3 Current Figure 7 19 SUB IDLE IDD4 Current 0 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 2 7V 3 0V 3 3V 4 5V 5 0V 5 5V uA 40 25 85 0 00 5 00 10 00 15 00 20 00...

Page 51: ...Z51F3220 Product Specification PS029902 0212 P R E L I M I N A R Y 48 Figure 7 20 STOP IDD5 Current 0 00 1 00 2 00 3 00 4 00 5 00 2 7V 3 0V 3 3V 4 5V 5 0V 5 5V uA 40 25 85...

Page 52: ...is capable of addressing up to 64k bytes but this device has just 32k bytes program memory space Figure 8 1 shows the map of the lower part of the program memory After reset the CPU begins execution...

Page 53: ...Z51F3220 Product Specification PS029902 0212 P R E L I M I N A R Y 50 FFFFH 0000H 32k Bytes 7FFFH 32k Bytes Including Interrupt Vector Region Figure 8 1 Program Memory...

Page 54: ...8 2 shows the upper 128 bytes and SFR space occupying the same block of addresses 80H through FFH although they are physically separate entities The lower 128 bytes of RAM are present in all 8051 devi...

Page 55: ...ister Bank 0 8 Bytes 07H 00H 8 Bytes R7 R6 R5 R4 R3 R2 R1 R0 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 5...

Page 56: ...es XRAM This area has no relation with RAM Flash It can be read and written to through SFR with 8 bit unit External RAM 768 Bytes Indirect Addressing LCD Display RAM 0000H 001AH 001BH 02FFH 107FH 1000...

Page 57: ...USI0CR1 USI0CR2 USI0CR3 USI0CR4 USI0SAR P0DB P15DB 0D0H PSW P5IO P0FSRL P0FSRH P1FSRL P1FSRH P2FSRL P2FSRH 0C8H OSCCR P4IO 0C0H EIFLAG0 P3IO T2CRL T2CRH T2ADRL T2ADRH T2BDRL T2BDRH 0B8H IP P2IO T1CRL...

Page 58: ...0CH 05H 0DH 06H 0EH 07H 0FH 1078H 1070H 1068H 1060H 1058H 1050H 1048H 1040H 1038H 1030H 1028H 1020H 1018H 1010H T4DLYA T4DLYB T4DLYC T4DR T4CAPR T4CNT 1008H T4PPRL T4PPRH T4ADRL T4ADRH T4BDRL T4BDRH...

Page 59: ...mer Control Register WDTCR R W 0 0 0 0 0 8EH Watch Dog Timer Data Register WDTDR W 1 1 1 1 1 1 1 1 Watch Dog Timer Counter Register WDTCNT R 0 0 0 0 0 0 0 0 8FH BUZZER Data Register BUZDR R W 1 1 1 1...

Page 60: ...ADH P1 Pull up Resistor Selection Register P1PU R W 0 0 0 0 0 0 0 0 AEH P2 Pull up Resistor Selection Register P2PU R W 0 0 0 0 0 0 0 0 AFH P3 Pull up Resistor Selection Register P3PU R W 0 0 0 0 0 0...

Page 61: ...H Reserved CFH Reserved D0H Program Status Word Register PSW R W 0 0 0 0 0 0 0 0 D1H P5 Direction Register P5IO R W 0 0 0 0 0 0 D2H P0 Function Selection Low Register P0FSRL R W 0 0 0 0 0 0 0 D3H P0 F...

Page 62: ...0 0 0 0 0 EDH USI1 Slave Address Register USI1SAR R W 0 0 0 0 0 0 0 0 EEH P3 Function Selection Register P3FSR R W 0 0 0 0 0 0 0 0 EFH P4 Function Selection Register P4FSR R W 0 0 0 0 0 0 0 F0H B Regi...

Page 63: ...Mask Register T4MSK R W 0 0 0 0 0 1008H Timer 4 PWM Period Low Register T4PPRL R W 1 1 1 1 1 1 1 1 1009H Timer 4 PWM Period High Register T4PPRH R W 0 0 100AH Timer 4 PWM A Duty Low Register T4ADRL R...

Page 64: ...5 4 3 2 1 0 B R W R W R W R W R W R W R W R W Initial value 00H B B Register SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer...

Page 65: ...Initial value 00H CY Carry Flag AC Auxiliary Carry Flag F0 General Purpose User Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P...

Page 66: ...ome bits are set by a system reset 9 2 3 Pull up Resistor Selection Register PxPU The on chip pull up resistor can be connected to I O ports individually with a pull up resistor selection register PxP...

Page 67: ...Selection High Register P1FSRL D4H R W 00H P1 Function Selection Low Register P2 90H R W 00H P2 Data Register P2IO B9H R W 00H P2 Direction Register P2PU AEH R W 00H P2 Pull up Resistor Selection Regi...

Page 68: ...nitial value 00H P0 7 0 I O Data P0IO P0 Direction Register A1H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R W R W R W R W R W R W R W R W Initial value 00H P0IO 7 0 P0 Data I O D...

Page 69: ...ebounce of P06 Port 0 Disable 1 Enable P05DB Configure Debounce of P05 Port 0 Disable 1 Enable P04DB Configure Debounce of P04 Port 0 Disable 1 Enable P03DB Configure Debounce of P03Port 0 Disable 1 E...

Page 70: ...alue 00H P1 7 0 I O Data P1IO P1 Direction Register B1H 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R W R W R W R W R W R W R W R W Initial value 00H P1IO 7 0 P1 Data I O Direction...

Page 71: ...ounce of P16 Port 0 Disable 1 Enable P12DB Configure Debounce of P12 Port 0 Disable 1 Enable P11DB Configure Debounce of P11 Port 0 Disable 1 Enable NOTES 1 If the same level is not detected on enable...

Page 72: ...lue 00H P2 7 0 I O Data P2IO P2 Direction Register B9H 7 6 5 4 3 2 1 0 P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO R W R W R W R W R W R W R W R W Initial value 00H P2IO 7 0 P2 Data I O Direction...

Page 73: ...P3 P3 P3 Data Register 98H 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 R W R W R W R W R W R W R W R W Initial value 00H P3 7 0 I O Data P3IO P3 Direction Register C1H 7 6 5 4 3 2 1 0 P37IO P36IO...

Page 74: ...0 P43 P42 P41 P40 R W R W R W R W Initial value 00H P4 3 0 I O Data P4IO P4 Direction Register C9H 7 6 5 4 3 2 1 0 P43IO P42IO P41IO P40IO R W R W R W R W Initial value 00H P4IO 3 0 P4 Data I O Direct...

Page 75: ...P5 P5 P5 Data Register B0H 7 6 5 4 3 2 1 0 P55 P54 P53 P52 P51 P50 R W R W R W R W R W R W Initial value 00H P5 5 0 I O Data P5IO P5 Direction Register D1H 7 6 5 4 3 2 1 0 P55IO P54IO P53IO P52IO P51...

Page 76: ...P0FSRH2 P0FSRH1 P0FSRH0 R W R W R W R W R W R W Initial value 00H P0FSRH 5 4 P07 Function Select P0FSRH5 P0FSRH4 Description 0 0 I OPort EINT5 function possible when input 0 1 SEG22 Function 1 0 AN5 F...

Page 77: ...iption 0 0 I OPort EINT2 function possible when input 0 1 SEG25 Function 1 0 AN2 Function 1 1 PWM4BA Function P0FSRL 4 3 P03 Function Select P0FSRL4 P0FSRL3 Description 0 0 I OPort EINT1 function poss...

Page 78: ...0 I OPort EINT6 SS2 function possible when input 0 1 SEG21 Function 1 0 AN6 Function 1 1 Not used P1FSRH 5 4 P16 Function Select P1FSRH5 P1FSRH4 Description 0 0 I OPort EINT7 function possible when i...

Page 79: ...ble when input 0 1 SEG17 Function 1 0 AN10 Function 1 1 BUZO Function P1FSRL 5 4 P12Function Select P1FSRL5 P1FSRL4 Description 0 0 I OPort EINT11 function possible when input 0 1 SEG16 Function 1 0 A...

Page 80: ...egister D7H 7 6 5 4 3 2 1 0 P2FSRH3 P2FSRH2 P2FSRH1 P2FSRH0 R W R W R W R W Initial value 00H P2FSRH3 P27 Function select 0 I OPort 1 SEG6 Function P2FSRH2 P26 Function Select 0 I OPort 1 SEG7 Functio...

Page 81: ...value 00H P2FSRL5 P23 Function Select 0 I OPort 1 SEG10 Function P2FSRL4 P22Function Select 0 I OPort SS1 function possible when input 1 SEG11 Function P2FSRL 3 2 P21 Function Select P2FSRL3 P2FSRL2...

Page 82: ...on Select 0 I OPort 1 COM3 SEG1 Function P3FSR3 P33 Function select 0 I OPort 1 COM4 SEG2 or COM0 Function P3FSR2 P32 Function Select 0 I OPort 1 COM5 SEG3 or COM1 Function P3FSR1 P31 Function select...

Page 83: ...on Select 0 I OPort SS0 function possible when input 1 VLC0 Function P4FSR 5 4 P42 Function Select P4FSR5 P4FSR4 Description 0 0 I OPort 0 1 VLC1 Function 1 0 SCK0 Function 1 1 Not used P4FSR 3 2 P41...

Page 84: ...4 Function Select 0 I OPort EINT10 function possible when input 1 SXOUT Function P5FSR 4 3 P53 Function Select P5FSR4 P5FSR3 Description 0 0 I OPort 0 1 SXIN Function 1 0 T0O PWM0O Function 1 1 Not us...

Page 85: ...interrupts are disabled when EA is set to 1 interrupts are individually enabled or disabled through the other bits of the interrupt enable registers The EA bit is always cleared to 0 jumping to an int...

Page 86: ...external interrupt source has enable disable bits The External interrupt flag 0 register EIFLAG0 and external interrupt flag 1 register 1 EIFLAG1 provides the status of external interrupts EINT1 Pin E...

Page 87: ...EIFLAG0 5 EIFLAG0 6 EIFLAG0 7 Timer 0 overflow Timer 0 Timer 1 Timer 2 Timer 3 IP1 IP IE FLAG10 FLAG11 IE2 T0OVIFR T0IFR T1IFR T2IFR T3IFR FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 EIPOL1 USI0...

Page 88: ...T15 IE2 3 16 Maskable 007BH T3 Match Interrupt INT16 IE2 4 17 Maskable 0083H T4 Interrupt INT17 IE2 5 18 Maskable 008BH ADC Interrupt INT18 IE3 0 19 Maskable 0093H SPI 2 Interrupt INT19 IE3 1 20 Maska...

Page 89: ...ing ISR IE EA Flag 0 1 Program Counter low Byte SP SP 1 M SP PCL 2 Program Counter high Byte SP SP 1 M SP PCH 3 Interrupt Vector Address occurrence Interrupt Vector Address 4 ISR Interrupt Service Rou...

Page 90: ...Effective Timing of Interrupt Enable Register Case b Interrupt flag Register Figure 10 5 Effective Timing of Interrupt Flag Register Interrupt Flag Register Command Next Instruction Next Instruction A...

Page 91: ...higher priority than INT1 is occurred Then INT0 is served immediately and then the remain part of INT1 service routine is executed If the priority level of INT0 is same or lower than INT1 INT0 will be...

Page 92: ...gisters Figure 10 9 Saving Restore Process Diagram and Sample Source Main Task Saving Register Restoring Register Interrupt Service Task INTxx PUSH PSW PUSH DPL PUSH DPH PUSH B PUSH ACC Interrupt_Proc...

Page 93: ...r Overview 10 12 1 Interrupt Enable Register IE IE1 IE2 IE3 Interrupt enable register consists of global interrupt control bit EA and peripheral interrupt control bits Total 24 peripherals are able to...

Page 94: ...rrupt generating condition is satisfied The flag is cleared when the interrupt service routine is executed Alternatively the flag can be cleared by writing 0 to it 10 12 4 External Interrupt Polarity...

Page 95: ...egister EIPOL0H A5H R W 00H External Interrupt Polarity 0 High Register EIFLAG1 A6H R W 00H External Interrupt Flag 1 Register EIPOL1 A7H R W 00H External Interrupt Polarity 1 Register 10 13 Interrupt...

Page 96: ...l Interrupt bits 0 All Interrupt disable 1 All Interrupt enable INT5E Enable or Disable External Interrupt 0 7 EINT0 EINT7 0 Disable 1 Enable INT4E Enable or Disable USI1 Tx Interrupt 0 Disable 1 Enab...

Page 97: ...W R W R W R W Initial value 00H INT11E Enable or Disable External Interrupt 12 EINT12 0 Disable 1 Enable INT10E Enable or Disable USI0 Tx Interrupt 0 Disable 1 Enable INT9E Enable or Disable USI0 Rx I...

Page 98: ...ble or Disable Timer 1 Match Interrupt 0 Disable 1 Enable INT13E Enable or Disable Timer 0 I Match nterrupt 0 Disable 1 Enable INT12E Enable or Disable Timer 0 Overflow Interrupt 0 Disable 1 Enable IE...

Page 99: ...P5 IP4 IP3 IP2 IP1 IP0 R W R W R W R W R W R W Initial value 00H IP1 Interrupt Priority Register 1 F8H 7 6 5 4 3 2 1 0 IP15 IP14 IP13 IP12 IP11 IP10 R W R W R W R W R W R W Initial value 00H IP 5 0 IP...

Page 100: ...5 4 3 2 1 0 POL7 POL6 POL5 POL4 R W R W R W R W R W R W R W R W Initial value 00H EIPOL0H 7 0 External interrupt EINT7 EINT6 EINT5 EINT4 polarity selection POLn 1 0 Description 0 0 No interrupt at an...

Page 101: ...T3IFR When T3 interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or automatically clear by INT_ACK signal 0 T3 Interrupt no generation 1 T3 Interrupt generation EIFLAG1 3 0 When...

Page 102: ...Hz INT RC Oscillator and the default division rate is eight In order to stabilize system internally it is used 1MHz INT RC oscillator on POR Calibrated Internal RC Oscillator 16 MHz INT RC OSC 1 16 MH...

Page 103: ...The clock generator register uses clock control for system operation The clock generation consists of System and clock control register and oscillator control register 11 1 5 Register Description for...

Page 104: ...RC 32 0 5MHz 0 0 1 INT RC 16 1MHz 0 1 0 INT RC 8 2MHz 0 1 1 INT RC 4 4MHz 1 0 0 INT RC 2 8MHz 1 0 1 INT RC 1 16MHz Other values Not used IRCE Control the Operation of the Internal RC Oscillator 0 Ena...

Page 105: ...g timer counting It also provides a basic interval timer interrupt BITIFR The Z51F3220 has these basic interval timer BIT features During Power On BIT gives a stable clock generation time On exiting S...

Page 106: ...ster Description The basic interval timer register consists of basic interval timer counter register BITCNT and basic interval timer control register BITCR If BCLR bit is set to 1 BITCNT becomes 0 and...

Page 107: ...ion 1 BIT interrupt generation BITCK 1 0 Select BIT clock source BITCK1 BITCK0 Description 0 0 fx 4096 0 1 fx 1024 1 0 fx 128 1 1 fx 16 BCLR If this bit is written to 1 BIT Counter is cleared to 0 0 F...

Page 108: ...eared and counts up After 1 machine cycle this bit is cleared to 0 automatically The watchdog timer consists of 8 bit binary counter and the watchdog timer data register When the value of 8 bit binary...

Page 109: ...1 3 4 Register Map Table 11 3 Watch Dog Timer Register Map Name Address Dir Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8D...

Page 110: ...Interrupt Interval x WDTDR Value 1 NOTE Do not write 0 in the WDTDR register WDTCR Watch Dog Timer Control Register 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL WDTCK WDTIFR R W R W R W R W R W Initial val...

Page 111: ...ounter circuits may be composed of 21 bit counter which contains low 14 bit with binary counter and high 7 bit counter in order to raise resolution In WTDR it can control WT clear and set interval val...

Page 112: ...ble register WTCR can control the clock source WTCK 1 0 interrupt interval WTIN 1 0 and function enable disable WTEN Also there is WT interrupt flag bit WTIFR 11 4 5 Register Description for Watch Tim...

Page 113: ...this bit or automatically clear by INT_ACK signal 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval WTIN1 WTIN0 Description 0 0 fWCK 2 7 0 1 fWCK 2 13 1 0 fW...

Page 114: ...an internal or an external clock source EC0 The clock source is selected by clock selection logic which is controlled by the clock selection bits T0CK 2 0 TIMER 0 clock source fX 2 4 8 32 128 512 2048...

Page 115: ...e T0CC The external clock EC0 counts up the timer at the rising edge If the EC0 is selected as a clock source by T0CK 2 0 EC0 port should be set to the input port by P52IO bit P r e s c a l e r fx M U...

Page 116: ...terrupt of timer 0 occurs In PWM mode the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H The timer 0 overflow interrup...

Page 117: ...XX T0CNT T0PWM 00H 01H 02H 4AH FFH FEH 00H T0 Match Interrupt T0 Overflow Interrupt T0DR 1 T0DR 4AH Timer 0 clock Set T0EN T0PWM T0 Match Interrupt 2 T0DR 00H T0PWM T0 Match Interrupt 3 T0DR FFH PWM...

Page 118: ...timer 0 output T0O waveform is not available According to EIPOL1 registers setting the external interrupt EINT10 function is chosen Of cource the EINT10 pin must be set to an input port T0CDR and T0D...

Page 119: ...ress Timer Overflow in Capture Mode T0CNT Interrupt Request FLAG10 XXH Interrupt Interval Period FFH 01H FFH 01H YYH 01H Ext EINT10 PIN Interrupt Request T0IFR FFH FFH YYH 00H 00H 00H 00H 00H T0CNT Va...

Page 120: ...fx 512 fx 2048 3 T0CK 2 0 T0EN 8 bit Timer 0 Counter T0DR 8Bit Comparator T0IFR To interrupt block T0O PWM0O 8 bit Timer 0 Data Register INT_ACK Clear Clear Match MUX T0CDR 8Bit Clear T0OVIFR To inte...

Page 121: ...ister T0CDR and timer 0 control register T0CR T0IFR and T0OVIFR bits are in the external interrupt flag 1 register EIFLAG1 11 5 6 2 Register Description for Timer Counter 0 T0CNT Timer 0 Counter Regis...

Page 122: ...0 Timer counter mode 0 1 PWM mode 1 x Capture mode T0CK 2 0 Select Timer 0 clock source fx is a system clock frequency T0CK2 T0CK1 T0CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1 fx 32 1 0 0...

Page 123: ...mode Also Ttimer 1 outputs PWM wave form through PWM1O port in the PPG mode Table 11 7 Timer 1 Operating Modes T1EN P1FSRL 5 4 T1MS 1 0 T1CK 2 0 Timer 1 1 11 00 XXX 16 Bit Timer Counter Mode 1 00 01...

Page 124: ...NT_ACK Clear To interrupt block A Match Buffer Register A A Match T1CC Reload Pulse Generator T1O R T1EN 3 T1CK 2 0 2 T1MS1 T1MS0 T1CC 0 0 X T1CK2 T1CRL X ADDRESS BAH INITIAL VALUE 0000_0000B T1CK1 T1...

Page 125: ...ed into T1BDRH T1BDRL According to EIPOL1 registers setting the external interrupt EINT11 function is chosen Of cource the EINT11 pin must be set as an input port A Match T1CC T1EN P r e s c a l e r f...

Page 126: ...r Overflow in Capture Mode T1CNTH L Interrupt Request FLAG11 XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT11 PIN Interrupt Request T1IFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H T1CNTH...

Page 127: ...X fx 2 fx 4 fx 64 fx 512 fx 2048 fx 8 fx 1 Comparator 16 bit Counter T1CNTH T1CNTL 16 bit B Data Register T1BDRH T1BDRL Clear B Match Edge Detector T1ECE EC1 Buffer Register B Comparator 16 bit A Data...

Page 128: ...1 M A Match 1 T1BDRH L 5 T1ADRH L PWM1O A Match 2 T1BDRH L T1ADRH L PWM1O A Match 3 T1BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 M 0 Timer 1 clock Counter T1ADRH L T1 Interrupt PWM1O B Match One shot M...

Page 129: ...T1O PWM1O R EINT11 T1CNTR T1EN 3 T1CK 2 0 Clear EIPOL1 5 4 FLAG11 EIFLAG1 2 INT_ACK Clear To interrupt block 2 2 T1MS 1 0 2 Edge Detector T1ECE EC1 To Timer 2 block A Match T1CC T1EN A Match T1CC T1E...

Page 130: ...W R W R W R W R W R W R W R W Initial value FFH T1ADRH 7 0 T1 A Data High Byte T1ADRL Timer 1 A Data Low Register BCH 7 6 5 4 3 2 1 0 T1ADRL7 T1ADRL6 T1ADRL5 T1ADRL4 T1ADRL3 T1ADRL2 T1ADRL1 T1ADRL0 R...

Page 131: ...1 0 Timer 1 disable 1 Timer 1 enable Counter clear and start T1MS 1 0 Control Timer 1 Operation Mode T1MS1 T1MS0 Description 0 0 Timer counter mode T1O toggle at A match 0 1 Capture mode The A match i...

Page 132: ...1 0 fx 1 1 1 1 External clock EC1 T1IFR When T1 Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal 0 T1 Interrupt no generation 1 T1 Interrupt gen...

Page 133: ...om prescaler output and T1 A Match timer 1 A match signal The clock source is selected by clock selection logic which is controlled by the clock selection bits T2CK 2 0 TIMER 2 clock source fX 1 2 4 8...

Page 134: ...atch signal is generated and the interrupt of Timer 2 occurs The T2CNTH T2CNTL values are automatically cleared by match signal It can be also cleared by software T2CC T2MS 1 0 T2POL A Match T2CC T2EN...

Page 135: ...M I N A R Y 132 Figure 11 23 16 Bit Timer Counter 2 Example T2CNTH L Value Timer 2 T2IFR Interrupt TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Period PCP x n 1 0 Count Pulse Period PCP Up count Match with T2...

Page 136: ...r 2 capture mode timer 2 output T2O waveform is not available According to EIPOL1 registers setting the external interrupt EINT12 function is chosen Of cource the EINT12 pin must be set to an input po...

Page 137: ...r Overflow in Capture Mode T2CNTH L Interrupt Request FLAG12 XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT12 PIN Interrupt Request T2IFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H T2CNTH...

Page 138: ...e r fx M U X fx 2 fx 4 fx 32 fx 128 fx 512 fx 8 fx 1 Comparator 16 bit Counter T2CNTH T2CNTL 16 bit B Data Register T2BDRH T2BDRL Clear B Match T1 A Match Buffer Register B Comparator 16 bit A Data Re...

Page 139: ...1 M A Match 1 T2BDRH L 5 T2ADRH L PWM2O A Match 2 T2BDRH L T2ADRH L PWM2O A Match 3 T2BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 M 0 Timer 2 clock Counter T2ADRH L T2 Interrupt PWM2O B Match One shot M...

Page 140: ...ulse Generator T2O PWM2O R EINT12 T2CNTR T2EN 3 T2CK 2 0 Clear EIPOL1 7 6 FLAG12 EIFLAG1 3 INT_ACK Clear To interrupt block 2 2 T2MS 1 0 2 T1 A Match A Match T2CC T2EN A Match T2CC T2EN Figure 11 29 1...

Page 141: ...R W R W R W R W R W R W R W R W Initial value FFH T2ADRH 7 0 T2 A Data High Byte T2ADRL Timer 2 A Data Low Register C4H 7 6 5 4 3 2 1 0 T2ADRL7 T2ADRL6 T2ADRL5 T2ADRL4 T2ADRL3 T2ADRL2 T2ADRL1 T2ADRL0...

Page 142: ...2 0 Timer 2 disable 1 Timer 2 enable Counter clear and start T2MS 1 0 Control Timer 2 Operation Mode T2MS1 T2MS0 Description 0 0 Timer counter mode T2O toggle at A match 0 1 Capture mode The A match i...

Page 143: ...0 1 0 fx 32 0 1 1 fx 8 1 0 0 fx 4 1 0 1 fx 2 1 1 0 fx 1 1 1 1 T1 A Match T2IFR When T2 Match Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal 0...

Page 144: ...d by the clock selection bits T3CK 2 0 T4CK 3 0 Also the timer counter 4 can use more clock sources than timer counter 3 TIMER 3 clock source fX 2 4 8 32 128 512 2048 and EC3 TIMER 4 clock source fX 1...

Page 145: ...imer at the rising edge If the EC3 is selected as a clock source by T3CK 2 0 EC3 port should be set to the input port by P00IO bit Timer 4 can t use the external EC3 clock T3EN T3CR 1 ADDRESS 1000H ES...

Page 146: ...CK 2 0 and 16BIT bit must be set to 1 Timer 3 is LSB 8 bit the timer 4 is MSB 8 bit The external clock EC3 counts up the timer at the rising edge f the EC3 is selected as a clock source by T3CK 2 0 EC...

Page 147: ...alue is automatically cleared by match signal This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer The capture result i...

Page 148: ...4 T4CK 3 0 8 bit Timer 4 Counter T4DR 8Bit Comparator To interrupt block T4O 8 bit Timer 4 Data Register Clear Match T4CAPR 8Bit Clear EINT1 EIPOL0L 3 2 FLAG0 EIFLAG0 1 S W Clear To interrupt block 2...

Page 149: ...T4CNT T3CNT 16Bit EC3 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T3CK 2 0 T3CN 16 bit Timer 3 Counter T4DR T3DR 16Bit Comparator T3IFR To interrupt block T3O 16 bit Timer 3 Data Register INT_ACK Clear Cl...

Page 150: ...A ch T4ADRH T4ADRL X Source Clock Table 11 12 PWM Frequency vs Resolution at 8 MHz Resolution Frequency T4CK 3 0 0001 250ns T4CK 3 0 0010 500ns T4CK 3 0 0100 2us 10 Bit 3 9KHz 1 95KHz 0 49KHz 9 Bit 7...

Page 151: ...or 10 bit C Data Register T4CDRH T4CDRL PWM Output Control C ch PWM4CA PWM Delay Control C ch PWM4CB A Match B Match C Match Interrupt Generator A Match B Match C Match Bottom Underflow To interrupt b...

Page 152: ...WM Output Control C ch PWM4CA PWM Delay Control C ch PWM4CB A Match Interrupt Generator A Match B Match C Match Bottom Underflow To interrupt block FORCA T4PCR2 1 ADDRESS 1004H ESFR INITIAL VALUE 0000...

Page 153: ...nternal clock synchronization circuit So the update data is written before 3 cycle of timer clock to get the right output waveform T4CNT 00 01 02 03 04 P02 PWM4AA POLAA 1 T4CR 03H 2us T4PPRH 00H T4PPR...

Page 154: ...Figure 11 39 Example of PWM waveform in Back to Back mode at 4 MHz T4CNT 00 01 02 03 04 P02 PWM4AA POLAA 1 T4CR 03H 2us T4PPRH 00H T4PPRL 0BH T4ADRH 00H T4ADRL 05H 09 08 07 06 05 0A 0B 0B 0A 06 07 08...

Page 155: ...sible to stop PWM operation by the software During PHLT bit being 1 PWM output becomes a reset value and internal counter becomes reset as 0 Without changing PWM setting temporarily it is able to stop...

Page 156: ...It is noted that the inversion outputs of A B C channel have the same A ch output waveform According to POLAA BB CC it is able to control the inversion of outputs Figure 11 42 Example of Force Drive...

Page 157: ...duty register a BA BB output of the B channel duty register a CA CB output of the C channel duty register are controlled respectively If the UALL bit is set to 1 it is updated B C channel duty at the...

Page 158: ...the falling edge so the duty is reduced as the time delay In POLAA BA CA setting to 0 the delay is applied to the falling edge In POLAA BA CA setting to 1 the delay is applied to the rising edge It ca...

Page 159: ...S 1010H ESFR INITIAL VALUE 0000_0000B FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE T4PCR2 0 X X X X X X HZCLR POLBO POLAA POLAB POLBA POLBB POLCA T4PCR3 X X 1 1 X X X X T4DLYAA3 T4DLYAA2 T4DLYAA1 T4DLYAA...

Page 160: ...R 8Bit Clear EINT0 EIPOL0L 1 0 FLAG0 EIFLAG0 0 INT_ACK Clear To interrupt block 2 T3MS T3ST 8 bit Timer 3 Capture Register T4CNT 8Bit 4 T4CK 3 0 8 bit Timer 4 Counter T4DR 8Bit Comparator To interrupt...

Page 161: ...s c a l e r fx M U X fx 2 fx 4 fx 16 fx 32 fx 64 fx 8 fx 1 Comparator 10 bit Counter 2Bit T4CNT 10 bit A Data Register T4ADRH T4ADRL Control Up Down Comparator T4PPRH T4PPRL 10Bit Period Match PWM Ou...

Page 162: ...High Register T4BDRL 100CH ESFR R W 7FH Timer 4 PWM B Duty Low Register T4CDRH 100FH ESFR R W 00H Timer 4 PWM C Duty High Register T4CDRL 100EH ESFR R W 7FH Timer 4 PWM C Duty Low Register T4DLYA 1010...

Page 163: ...er Register Read Case Timer mode only 1001H ESFR 7 6 5 4 3 2 1 0 T3CNT7 T3CNT6 T3CNT5 T3CNT4 T3CNT3 T3CNT2 T3CNT1 T3CNT0 R R R R R R R R Initial value 00H T3CNT 7 0 T3 Counter T3DR Timer 3 Data Regist...

Page 164: ...ode T3O toggle at match 1 Capture mode the match interrupt can occur T3CK 2 0 Select Timer 3 clock source fx is main system clock frequency T3CK2 T3CK1 T3CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx...

Page 165: ...gister T4ISR and timer 4 interrupt mask register T4MSK 11 8 8 4 Register Description for Timer Counter 4 T4PPRH Timer 4 PWM Period High Register 6 ch PWM mode only 1009H ESFR 7 6 5 4 3 2 1 0 T4PPRH1 T...

Page 166: ...Byte T4CDRL Timer 4 PWM C Duty Low Register 6 ch PWM mode only 100EH ESFR 7 6 5 4 3 2 1 0 T4CDRL7 T4CDRL6 T4CDRL5 T4CDRL4 T4CDRL3 T4CDRL2 T4CDRL1 T4CDRL0 R W R W R W R W R W R W R W R W Initial value...

Page 167: ...gister Timer and Capture mode only 1013H ESFR 7 6 5 4 3 2 1 0 T4DR7 T4DR6 T4DR5 T4DR4 T4DR3 T4DR2 T4DR1 T4DR0 R W R W R W R W R W R W R W R W Initial value FFH T4DR 7 0 T4 Data T4CAPR Timer 4 Capture...

Page 168: ...le at match 1 Capture mode the match interrupt can occur T4CN Control Timer 4 Count Pause Continue 0 Temporary count stop 1 Continue count T4ST Control Timer 4 Start Stop 0 Counter stop 1 Clear counte...

Page 169: ...edge of the BLNK input pin Where x A B and C BMOD Control Back to Back Mode Operation 0 Disable back to back mode up count only 1 Enable back to back mode up down count only PHLT Control Timer 4 PWM...

Page 170: ...all PWM4xA PWM4xB pins are output according to the only T4ADR registers Where x A B and C PAAOE Select Channel PWM4AA Operation 0 Disable PWM4AA output 1 Enable PWM4AA output PABOE Select Channel PWM...

Page 171: ...polarity setting when disable POLAB POLBB POLCB bits where x A B and C POLAA Configure PWM4AA Channel Polarity 0 Start at high level This pin is low level when disable 1 Start at low level This pin i...

Page 172: ...m B ch match occurrence 1 PWm B ch match no occurrence ICMC Timer 4 PWM C ch Match Interrupt Status Write 1 to this bit for clear 0 PWm C ch match occurrence 1 PWm C ch match no occurrence T4MSK Timer...

Page 173: ...lects source clock divided by prescaler Table 11 15 Buzzer Frequency at 8 MHz BUZDR 7 0 Buzzer Frequency kHz BUZCR 2 1 00 BUZCR 2 1 01 BUZCR 2 1 10 BUZCR 2 1 11 0000_0000 125kHz 62 5kHz 31 25kHz 15 62...

Page 174: ...escription for Buzzer Driver BUZDR Buzzer Data Register 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDR 7 0 This bit...

Page 175: ...CK2 SS2 support master slave mode can select serial clock SCK2 polarity phase and whether LSB first data transfer or MSB first data transfer 11 10 2 Block Diagram P r e s c a l e r fx M U X fx 4 fx 8...

Page 176: ...ister SPIDR 11 10 4 SS2 pin function 1 When the SPI 2 is configured as a Slave the SS2 pin is always input If LOW signal come into SS2 pin the SPI 2 logic is active And if HIGH signal come into SS2 pi...

Page 177: ...MOSI2 MISO2 Input D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SCK2 CPOL 0 SS2 SPIIFR Figure 11 50 SPI 2 Transmit Receive Timing Diagram at CPHA 0 SCK2 CPOL 1 MISO2 MOSI2 Output MOSI2 MISO2 Input D...

Page 178: ...ontrol Register 11 10 7 SPI 2 Register Description The SPI 2 register consists of SPI 2 control register SPICR SPI 2 status register SPISR and SPI 2 data register SPIDR 11 10 8 Register Description fo...

Page 179: ...SPIDR 0 SPI 2 Interrupt no generation 1 SPI 2 Interrupt generation WCOL This bit is set if any data are written to the data register SPIDR during transfer This bit is cleared when the status register...

Page 180: ...de CPOL CPHA This two bits control the serial clock SCK2 mode Clock polarity CPOL bit determine SCK2 s value at idle mode Clcok phase CPHA bit determine if data are sampled on the leading or trailing...

Page 181: ...bits should be set to xxx The register ADCDRH and ADCDRL contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCDRH and ADCDRL the A D conversion...

Page 182: ...oltage AVREF AVSS AN1 AN2 AN14 AN15 ADCIFR AFLAG INT_ACK Clear Clear To interrupt block MUX VDD Start M U X T4 A match event signal T4 B match event signal T4 C match event signal REFSEL TRIG 2 0 3 AD...

Page 183: ...CO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCO11 ADCO10 AD...

Page 184: ...R W 00H A D Converter Control Low Register 11 11 6 ADC Register Description The ADC register consists of A D converter data high register ADCDRH A D converter data low register ADCDRL A D converter c...

Page 185: ...r Low Data 8 bit ADCCRH A D Converter High Register 9DH 7 6 5 4 3 2 1 0 ADCIFR TRIG2 TRIG1 TRIG0 ALIGN CKSEL1 CKSEL0 R W R W R W R W R W R W R W Initial value 00H ADCIFR When ADC interrupt occurs this...

Page 186: ...0 No effect 1 ADC Conversion Start and auto clear REFSEL A D Converter Reference Selection 0 Internal Reference VDD 1 External Reference AVREF AFLAG A D Converter Operation State This bit is cleared...

Page 187: ...gister USI0 data register USI0 SDA hold time register USI0 SCL high period register USI0 SCL low period register and USI0 slave address register USI0CR1 USI0CR2 USI0CR3 USI0CR4 USI0ST1 USI0ST2 USI0BD...

Page 188: ...n parts of clock generator Transmitter and receiver The clock generation logic consists of synchronization logic for external clock inut used by synchronous or SPI slave operation and the baud rate ge...

Page 189: ...Generator Transmit Shift Register TXSR USI0DR USI0TX8 Tx USI0P 1 0 M U X LOOPS0 TXC0 TXCIE0 DRIE0 DRE0 Empty signal To interrupt block INT_ACK Clear RXC0 RXCIE0 WAKEIE0 WAKE0 At Stop mode To interrup...

Page 190: ...ous double speed mode is controlled by the DBLS0 bit in the USI0CR2 register The MASTER0 bit in USI0CR3 register controls whether the clock source is internal master mode output pin or external slave...

Page 191: ...mode operation When synchronous or SPI mode is used the SCK0 pin will be used as either clock input slave or clock output master Data sampling and transmitter is issued on the different edge of SCK0 c...

Page 192: ...e set to an idle state The idle means high state of data pin The following figure shows the possible combinations of the frame formats Bits inside brackets are optional Figure 11 60 Frame Format USI0...

Page 193: ...e USI0TX8 bit in USI0CR3 register before it is loaded to the transmit buffer USI0DR register 11 12 9 2 USI0 UART Transmitter flag and interrupt The UART transmitter has 2 flags which indicate its stat...

Page 194: ...SS0 input pin in slave mode or can be configured as SS0 output pin in master mode This can be done by setting USI0SSEN bit in USI0CR3 register 11 12 10 1 USI0 UART Receiving Rx data When UART is in s...

Page 195: ...first stop bit The FE0 flag is 0 when the stop bit was correctly detected as 1 and the FE0 flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync c...

Page 196: ...an 2 samples have logical low level it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame And the data recovery can begin Th...

Page 197: ...correct stop bit is detected else a frame error FE0 flag is set After deciding whether the first stop bit is valid or not the Receiver goes to idle state and monitors the RXD0 line to check a valid h...

Page 198: ...is renamed as MOSI0 for compatibility to other SPI devices 11 12 12 USI0 SPI Clock Formats and Timing To accommodate a wide variety if synchronus serial peripherals from different manufacturers the US...

Page 199: ...ISO0 and MOSI0 inputs respectively At the second SCK0 edge the USI0 shifts the second data bit value out to the MOSI0 and MISO0 outputs of the master and slave respectively Unlike the case of CPHA0 1...

Page 200: ...t value out to the MOSI0 and MISO0 output of the master and slave respectively When CPHA0 1 the slave s SS0 input is not required to go to its inactive high level between transfers Because the SPI log...

Page 201: ...egister TXSR USI0DR Tx I N T E R N A L B U S L I N E M U X LOOPS0 TXC0 TXCIE0 DRIE0 DRE0 Empty signal To interrupt block INT_ACK Clear RXC0 Baud Rate Generator USI0BD TXE0 SCLK fx System clock MISO0 M...

Page 202: ...mpatible with I2C bus standard Multi master operation Up to 400kHz data transfer read speed 7 bit address Both master and slave operation Bus busy detection 11 12 15 USI0 I2C Bit Transfer The data on...

Page 203: ...sy So the START and repeated START conditions are functionally identical Figure 11 68 START and STOP Condition USI0 11 12 17 USI0 I2C Data Transfer Every byte put on the SDA0 line must be 8 bits long...

Page 204: ...dge on the I2C Bus USI0 11 12 19 USI0 I2C Synchronization Arbitration Clock synchronization is performed using the wired AND connection of I2C interfaces to the SCL0 line This means that a HIGH to LOW...

Page 205: ...USI0CR4 register is set it is cleared by writing an any value to USI0ST2 When I2C interrupt occurs the SCL0 line is hold LOW until writing any value to USI0ST2 When the IIC0IFR flag is set the USI0ST...

Page 206: ...choose one of the following cases regardless of the reception of ACK signal from slave 1 Master receives ACK signal from slave so continues data transfer because slave can receive more data from mast...

Page 207: ...command or Data Write From slave to master 0xxx Value of Status Register ACK Interrupt SCL0 line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST Other...

Page 208: ...ication The following steps continue assuming that I2C does not lose mastership during first data transfer I2C Master can choose one of the following cases according to the reception of ACK signal fro...

Page 209: ...on of I2C can be depicted as the following figure Figure 11 74 Formats and States in the Master Receiver Mode USI0 From master to slave Master command or Data Write From slave to master 0xxx Value of...

Page 210: ...dle state ie waits for another START condition Else if the address equals to USI0SLA 6 0 bits and the ACK0EN bit is enabled I2C generates SSEL0 interrupt and the SCL0 line is held LOW Note that even i...

Page 211: ...es in the Slave Transmitter Mode USI0 SLA R ACK DATA LOST S or Sr Y 0x47 ACK STOP Y N 0x46 P 0x22 IDLE IDLE Y GCALL 0x1F 0x97 0x17 From master to slave Master command or Data Write From slave to maste...

Page 212: ...te ie waits for another START condition Else if the address equals to SLA0 bits and the ACK0EN bit is enabled I2C generates SSEL0 interrupt and the SCL0 line is held LOW Note that even if the address...

Page 213: ...States in the Slave Receiver Mode USI0 SLA W ACK DATA LOST S or Sr Y N 0x45 ACK STOP Y N 0x44 P 0x20 IDLE IDLE Y GCALL 0x1D 0x95 0x15 From master to slave Master command or Data Write From slave to m...

Page 214: ...oller USI0DR Tx Slave Address Register USI0SAR General Call And Address Detector USI0GCE STOP START Condition Generator STOPC0 STARTC0 ACK Signal Generator ACK0EN RXACK0 GCALL0 TEND0 STOPD0 SSEL0 MLOS...

Page 215: ...0 Register Description USI0 module consists of USI0 baud rate generation register USI0BD USI0 data register USI0DR USI0 SDA hold time register USI0SDHR USI0 SCL high period register USI0SCHR USI0 SCL...

Page 216: ...R W Initial value 00H USI0SDHR 7 0 The register is used to control SDA0 output timing from the falling edge of SCI in I2C mode NOTE That SDA0 is changed after tSCLK X USI0SDHR 2 in master SDA 0 chang...

Page 217: ...base clock is SCLK the system clock and the period is calculated by the formula tSCLK X 4 X USI0SCLR 2 where tSCLK is the period of SCLK USI0SAR USI0 Slave Address Register For I2C mode DDH 7 6 5 4 3...

Page 218: ...the length of data bits in frame USI0S2 USI0S1 USI0S0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit ORD0 This bit in the same bi...

Page 219: ...rupt from RXC0 is inhibited use polling 1 When RXC0 is set request an interrupt WAKEIE0 Interrupt enable bit for asynchronous wake in STOP mode When device is in stop mode if RXD0 goes to low level an...

Page 220: ...unning while UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring USI0SSEN This bit controls the SS0 pin operation only SPI mode 0 Disable 1 Enable The SS0 pin...

Page 221: ...r I2C mode 0 Interrupt from I2C is inhibited use polling 1 Enable interrupt for I2C ACK0EN Controls ACK signal Generation at ninth SCL0 period 0 No ACK signal is generated SDA0 1 1 ACK signal is gener...

Page 222: ...d to generate a RXC0 interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKE0 This flag is set when the RXD0 pin is detected low while the CPU...

Page 223: ...his bit is set when a STOP condition is detected 0 No STOP condition is detected 1 STOP condition is detected SSEL0 NOTE This bit is set when I2C is addressed by other master 0 I2C is not selected as...

Page 224: ...gister USI1 data register USI1 SDA hold time register USI1 SCL high period register USI1 SCL low period register and USI1 slave address register USI1CR1 USI1CR2 USI1CR3 USI1CR4 USI1ST1 USI1ST2 USI1BD...

Page 225: ...n parts of clock generator Transmitter and receiver The clock generation logic consists of synchronization logic for external clock inut used by synchronous or SPI slave operation and the baud rate ge...

Page 226: ...Generator Transmit Shift Register TXSR USI1DR USI1TX8 Tx USI1P 1 0 M U X LOOPS1 TXC1 TXCIE1 DRIE1 DRE1 Empty signal To interrupt block INT_ACK Clear RXC1 RXCIE1 WAKEIE1 WAKE1 At Stop mode To interrup...

Page 227: ...ous double speed mode is controlled by the DBLS1 bit in the USI1CR2 register The MASTER1 bit in USI1CR3 register controls whether the clock source is internal master mode output pin or external slave...

Page 228: ...mode operation When synchronous or SPI mode is used the SCK1 pin will be used as either clock input slave or clock output master Data sampling and transmitter is issued on the different edge of SCK1 c...

Page 229: ...e set to an idle state The idle means high state of data pin The following figure shows the possible combinations of the frame formats Bits inside brackets are optional Figure 11 81 Frame Format USI1...

Page 230: ...e USI1TX8 bit in USI1CR3 register before it is loaded to the transmit buffer USI1DR register 11 13 9 2 USI1 UART Transmitter flag and interrupt The UART transmitter has 2 flags which indicate its stat...

Page 231: ...SS1 input pin in slave mode or can be configured as SS1 output pin in master mode This can be done by setting USI1SSEN bit in USI1CR3 register 11 13 10 1 USI1 UART Receiving Rx data When UART is in s...

Page 232: ...first stop bit The FE1 flag is 0 when the stop bit was correctly detected as 1 and the FE1 flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync c...

Page 233: ...an 2 samples have logical low level it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame And the data recovery can begin Th...

Page 234: ...correct stop bit is detected else a frame error FE1 flag is set After deciding whether the first stop bit is valid or not the Receiver goes to idle state and monitors the RXD1 line to check a valid h...

Page 235: ...is renamed as MOSI1 for compatibility to other SPI devices 11 13 12 USI1 SPI Clock Formats and Timing To accommodate a wide variety if synchronus serial peripherals from different manufacturers the US...

Page 236: ...ISO1 and MOSI1 inputs respectively At the second SCK1 edge the USI1 shifts the second data bit value out to the MOSI1 and MISO1 outputs of the master and slave respectively Unlike the case of CPHA1 1...

Page 237: ...t value out to the MOSI1 and MISO1 output of the master and slave respectively When CPHA1 1 the slave s SS1 input is not required to go to its inactive high level between transfers Because the SPI log...

Page 238: ...egister TXSR USI1DR Tx I N T E R N A L B U S L I N E M U X LOOPS1 TXC1 TXCIE1 DRIE1 DRE1 Empty signal To interrupt block INT_ACK Clear RXC1 Baud Rate Generator USI1BD TXE1 SCLK fx System clock MISO1 M...

Page 239: ...mpatible with I2C bus standard Multi master operation Up to 400kHz data transfer read speed 7 bit address Both master and slave operation Bus busy detection 11 13 15 USI1 I2C Bit Transfer The data on...

Page 240: ...sy So the START and repeated START conditions are functionally identical Figure 11 89 START and STOP Condition USI1 11 13 17 USI1 I2C Data Transfer Every byte put on the SDA1 line must be 8 bits long...

Page 241: ...dge on the I2C Bus USI1 11 13 19 USI1 I2C Synchronization Arbitration Clock synchronization is performed using the wired AND connection of I2C interfaces to the SCL1 line This means that a HIGH to LOW...

Page 242: ...USI1CR4 register is set it is cleared by writing an any value to USI1ST2 When I2C interrupt occurs the SCL1 line is hold LOW until writing any value to USI1ST2 When the IIC1IFR flag is set the USI1ST...

Page 243: ...n choose one of the following cases regardless of the reception of ACK signal from slave 1 Master receives ACK signal from slave so continues data transfer because slave can receive more data from mas...

Page 244: ...command or Data Write From slave to master 0xxx Value of Status Register ACK Interrupt SCL1 line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST Other...

Page 245: ...unication The following steps continue assuming that I2C does not lose mastership during first data transfer I2C Master can choose one of the following cases according to the reception of ACK signal f...

Page 246: ...ion of I2C can be depicted as the following figure Figure 11 95 Formats and States in the Master Receiver Mode USI1 From master to slave Master command or Data Write From slave to master 0xxx Value of...

Page 247: ...le state ie waits for another START condition Else if the address equals to USI1SLA 6 0 bits and the ACK1EN bit is enabled I2C generates SSEL1 interrupt and the SCL1 line is held LOW Note that even if...

Page 248: ...es in the Slave Transmitter Mode USI1 SLA R ACK DATA LOST S or Sr Y 0x47 ACK STOP Y N 0x46 P 0x22 IDLE IDLE Y GCALL 0x1F 0x97 0x17 From master to slave Master command or Data Write From slave to maste...

Page 249: ...te ie waits for another START condition Else if the address equals to SLA1 bits and the ACK1EN bit is enabled I2C generates SSEL1 interrupt and the SCL1 line is held LOW Note that even if the address...

Page 250: ...States in the Slave Receiver Mode USI1 SLA W ACK DATA LOST S or Sr Y N 0x45 ACK STOP Y N 0x44 P 0x20 IDLE IDLE Y GCALL 0x1D 0x95 0x15 From master to slave Master command or Data Write From slave to m...

Page 251: ...oller USI1DR Tx Slave Address Register USI1SAR General Call And Address Detector USI1GCE STOP START Condition Generator STOPC1 STARTC1 ACK Signal Generator ACK1EN RXACK1 GCALL1 TEND1 STOPD1 SSEL1 MLOS...

Page 252: ...1 Register Description USI1 module consists of USI1 baud rate generation register USI1BD USI1 data register USI1DR USI1 SDA hold time register USI1SDHR USI1 SCL high period register USI1SCHR USI1 SCL...

Page 253: ...R W Initial value 00H USI1SDHR 7 0 The register is used to control SDA1 output timing from the falling edge of SCL1 in I2C mode NOTE That SDA1 is changed after tSCLK X USI1SDHR 2 in master SDA1 chang...

Page 254: ...base clock is SCLK the system clock and the period is calculated by the formula tSCLK X 4 X USI1SCLR 2 where tSCLK is the period of SCLK USI1SAR USI1 Slave Address Register For I2C mode EDH 7 6 5 4 3...

Page 255: ...the length of data bits in frame USI1S2 USI1S1 USI1S0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit ORD1 This bit in the same bi...

Page 256: ...rupt from RXC1 is inhibited use polling 1 When RXC1 is set request an interrupt WAKEIE1 Interrupt enable bit for asynchronous wake in STOP mode When device is in stop mode if RXD1 goes to low level an...

Page 257: ...unning while UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring USI1SSEN This bit controls the SS1 pin operation only SPI mode 0 Disable 1 Enable The SS1 pin...

Page 258: ...r I2C mode 0 Interrupt from I2C is inhibited use polling 1 Enable interrupt for I2C ACK1EN Controls ACK signal Generation at ninth SCL1 period 0 No ACK signal is generated SDA1 1 1 ACK signal is gener...

Page 259: ...d to generate a RXC1 interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKE1 This flag is set when the RXD1 pin is detected low while the CPU...

Page 260: ...his bit is set when a STOP condition is detected 0 No STOP condition is detected 1 STOP condition is detected SSEL1 NOTE This bit is set when I2C is addressed by other master 0 I2C is not selected as...

Page 261: ...4k continued Baud Rate fx 3 6864MHz fx 4 00MHz fx 7 3728MHz USI0BD USI1BD ERROR USI0BD USI1BD ERROR USI0BD USI1BD ERROR 2400 95 0 0 103 0 2 191 0 0 4800 47 0 0 51 0 2 95 0 0 9600 23 0 0 25 0 2 47 0 0...

Page 262: ...trolled by the LCD Control Register LCDCRH L The LCLK 1 0 determines the frequency of COM signal scanning of each segment output A RESET clears the LCD control register LCDCRH and LCDCRL values to log...

Page 263: ...the display data and drive method Therefore display patterns can be changed by only overwriting the contents of the display external data area with a program Figure 11 99 shows the correspondence bet...

Page 264: ...al Waveform 1 Frame VDD VSS 0 1 COM1 SEG1 COM0 SEG0 COM0 VSS VLC0 VLC2 VLC1 VLC3 COM0 COM1 SEG0 SEG1 SEG3 0 1 SEG2 SEG0 VSS VSS VLC0 VLC2 VLC1 VLC3 VLC2 VLC1 VLC3 VLC0 VSS VSS VLC0 VLC2 VLC1 VLC3 VLC0...

Page 265: ...1 SEG2 COM2 1 Frame VDD VSS 0 1 COM1 SEG2 COM0 SEG1 COM0 VLC2 VLC3 VLC0 VLC1 SEG1 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 2 0 1 2 VSS VLC2 VLC3 VLC0 VLC1 VSS COM2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1...

Page 266: ...COM3 COM2 1 Frame VDD VSS 0 1 COM1 SEG3 COM0 SEG2 COM0 VLC2 VLC3 VLC0 VLC1 SEG2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 2 VSS VLC2 VLC3 VLC0 VLC1 VSS COM2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC...

Page 267: ...7 S E G 8 S E G 9 S E G 1 0 1 Frame VDD VSS 0 COM1 SEG7 COM0 SEG6 COM0 VLC2 VLC0 VLC1 SEG6 VSS COM2 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VS...

Page 268: ...80K ohm VLC0 VLC1 VLC2 VLC3 LCTEN DISP VSS R VLC0 VLC1 VLC2 VLC3 VLCD 1 3 BIAS VLC0 VLC1 VLC2 VLC3 R Contrast Controller LCTEN DISP Cont rast Controller LCTEN DISP Contrast Cont roller LCTEN DISP Cont...

Page 269: ...the dividing resistors should be connected like the above figure and the needed bias pins should be selected as the LCD bias function pins VLC0 VLC1 VLC2 and VLC3 by P4FSR register When it is 1 2 bias...

Page 270: ...11 106 LCD Circuit Block Diagram 11 15 6 Register Map Table 11 26 LCD Register Map Name Address Dir Default Description LCDCRH 9AH R W 00H LCD Driver Control High Register LCDCRL 99H R W 00H LCD Drive...

Page 271: ...M0 COM3 signals are outputted through the P33 P30 NOTES 1 The COM0 COM1 COM2 COM3 signals can be outputted through the P33 P32 P31 P30 respectively 2 For example the COM0 signal may be outputted to P3...

Page 272: ...hm 0 0 1 0 1 5Duty 1 3Bias 60k ohm 0 0 1 1 1 4Duty 1 3Bias 60k ohm 0 1 0 0 1 3Duty 1 3Bias 60k ohm 0 1 0 1 1 3Duty 1 2Bias 60k ohm 0 1 1 0 1 3Duty 1 2Bias 120k ohm 0 1 1 1 1 2Duty 1 2Bias 60k ohm 1 0...

Page 273: ...LC0 VDD x 16 31 step 0 0 0 1 VLC0 VDD x 16 30 step 0 0 1 0 VLC0 VDD x 16 29 step 0 0 1 1 VLC0 VDD x 16 28 step 0 1 0 0 VLC0 VDD x 16 27 step 0 1 0 1 VLC0 VDD x 16 26 step 0 1 1 0 VLC0 VDD x 16 25 step...

Page 274: ...d with WDTRC OSC Watch Timer Operates Continuously Stop Can be operated with sub clock Timer0 4 Operates Continuously Halted Only when the Event Counter Mode is Enabled Timer operates Normally ADC Ope...

Page 275: ...ation continues and peripherals are operated normally but CPU stops It is released by reset or interrupt To be released by interrupt interrupt should be enabled before IDLE mode If using reset because...

Page 276: ...be operated with the sub clock The source for exit from STOP mode is hardware reset and interrupts The reset re defines all the control registers When exit from STOP mode enough oscillation stabiliza...

Page 277: ...is set to 1 the STOP mode is released by the interrupt which each interrupt enable flag 1 and the CPU jumps to the relevant interrupt service routine Even if the IE EA bit is cleared to 0 the STOP mo...

Page 278: ...Control Register 87H 7 6 5 4 3 2 1 0 PCON7 PCON3 PCON2 PCON1 PCON0 R W R W R W R W R W Initial value 00H PCON 7 0 Power Control 01H IDLE mode enable 03H STOP mode enable Other Values Normal operation...

Page 279: ...er Refer to the Peripheral Registers 13 2 Reset Source The Z51F3220 has five types of reset sources The following is the reset sources External RESETB Power ON RESET POR WDT Overflow Reset In the case...

Page 280: ...ET When rising device power the POR Power On Reset has a function to reset the device If POR is used it executes the device RESET function instead of the RESET IC or the RESET circuits Figure 13 3 Fas...

Page 281: ...eset Release Config Read POR VDD Input Internal OSC VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 8MHz 8 INT OSC 8MHz RESET_SYSB Config Read 1us X 256 X 28h about 10ms 1...

Page 282: ...input voltage must rise over than flash operating voltage for Config read Slew Rate 0 15V ms Config read point about 1 5V 1 6V Config Value is determined by Writing Option Rising section to Reset Rele...

Page 283: ...er the stable state the internal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure 13 7 Timing Diag...

Page 284: ...2 20V 2 32V 2 44V 2 59V 2 75V 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the LVREN...

Page 285: ...age Generator 2 59V 2 75V LVI Circuit LVILS 3 0 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V 2 10V 2 20V 2 32V 2 00V 4 Figure 13 12 LVI Diagram VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Re...

Page 286: ...eset RESETB flag bit The bit is reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection WDTRF Watch Dog Reset flag bit The bit is reset by writing 0 to this bit or by Power On R...

Page 287: ...le When this bit is 0 the LVREN bit is not effect by stop mode to release LVRVS 3 0 LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 0 0 0 0 1 60V 0 0 0 1 2 00V 0 0 1 0 2 10V 0 0 1 1 2 20V 0...

Page 288: ...nitial value 00H LVIF Low Voltage Indicator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVILS 3 0 LVI Level Select LVILS3 LVILS2 LVILS1 LVILS0 Description 0 0 0 0 2...

Page 289: ...ock input 1 wire bi directional serial data bus Debugger Access to All Internal Peripheral Units Internal data RAM Program Counter Flash and Data EEPROM Memories Extensive On chip Debug Support for Br...

Page 290: ...ransmitter Receiver generates acknowledge bit as 0 when transmission for 8 bit data and its parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is...

Page 291: ...nsfer Figure 14 3 Data Transfer on the Twin Bus 14 2 2 2 Bit Transfer Figure 14 4 Bit Transfer on the Serial Bus data line stable data valid except Start and Stop change of data allowed DSDA DSCL St S...

Page 292: ...ion Figure 14 5 Start and Stop Condition 14 2 2 4 Acknowledge Bit Figure 14 6 Acknowledge on the Serial Bus 1 9 2 10 Data output by transmitter Data output By receiver DSCL from master clock pulse for...

Page 293: ...14 7 Clock Synchronization during Wait Procedure Start wait start HIGH Host PC DSCL OUT Target Device DSCL OUT DSCL wait HIGH Maximum 5 TSCLK Internal Operation Acknowledge bit transmission minimum 1...

Page 294: ...ain wire AND bidirectional I O Figure 14 8 Connection of Transmission DSCL OUT DSDA OUT DSDA IN DSCL Debugger Serial Clock Line DSDA Debugger Serial Data Line DSDA OUT DSDA IN Host Machine Master Targ...

Page 295: ...be written erased and overwritten while mounted on the board The flash memory can be read by MOVC instruction and it can be programmed in OCD serial ISP mode or user program mode Flash Size 32kbytes S...

Page 296: ...s Sector 510 07F80H 07F7FH 07F40H Sector 509 07F40H 07F3FH Sector 508 Sector 2 00080H 0007FH 00040H Sector 1 00040H 0003FH 00000H Sector 0 00000H 00080H 8000H Flash Page Buffer External Data Memory 64...

Page 297: ...h Sector Address Low Register FIDR FDH R W 00H Flash Identification Register FMCR FEH R W 00H Flash Mode Control Register 15 1 4 Register Description for Flash Memory Control and Status Flash control...

Page 298: ...R W R W Initial value 00H FSADRM 7 0 Flash Sector Address Middle FSADRL Flash Sector Address Low Register FCH 7 6 5 4 3 2 1 0 FSADRL7 FSADRL6 FSADRL5 FSADRL4 FSADRL3 FSADRL2 FSADRL1 FSADRL0 R W R W R...

Page 299: ...and the global interrupt is on disable state regardless of the IE 7 EA bit FMCR2 FMCR1 FMCR0 Description 0 0 1 Select flash page buffer reset mode and start regardless of the FIDR value Clear all 64by...

Page 300: ...rotection areas are available only when the PAEN bit is cleared to 0 that is enable protection area at the configure option 2 if it is needed If the protection area isn t enabled PAEN 1 this area can...

Page 301: ...ion must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 64 Sector size is 64bytes MOV DPH 0x80 MOV DPL 0 Pgbuf_clr MOVX DPTR A INC DPTR DJNZ R0 Pgbuf_clr Write 0 to all...

Page 302: ...st be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV DPH 0x80 MOV DPL 0 MOVX DPTR A MOV DPH 0x80 MOV DPL 0x05 MOVX DPTR A Write 0 to page buffer MOV FSADRH 0x00 MOV FSADRM 0x...

Page 303: ...st be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 64 Sector size is 64bytes MOV DPH 0x80 MOV DPL 0 Pgbuf_WR MOVX DPTR A INC A INC DPTR DJNZ R0 Pgbuf_WR Write data to al...

Page 304: ...Dummy instruction This instruction must be needed MOV A 5 MOV DPH 0x80 MOV DPL 0 MOVX DPTR A Write data to page buffer MOV A 6 MOV DPH 0x80 MOV DPL 0x05 MOVX DPTR A Write data to page buffer MOV FSADR...

Page 305: ...x40 flash memory address MOVC A A DPTR read data from flash memory 15 1 11 Hard Lock Mode The Reading program procedure in user program mode 1 Set flash identification register FIDR 2 Set flash mode c...

Page 306: ...on 1 Enable Read protection HL Hard Lock 0 Disable Hard lock 1 Enable Hard lock RSTS RESETB Select 0 P55 port 1 RESETB port with a pull up resistor CONFIGURE OPTION 2 ROM Address 003EH 7 6 5 4 3 2 1 0...

Page 307: ...a Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 07 DEC A Decrem...

Page 308: ...t byte 2 2 86 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 A7 MOV Ri data Move immediate to i...

Page 309: ...re A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare indirect immediate jne relati...

Page 310: ...n t cause any error by using compare jump instructions If input signal is fixed there is no error in using compare jump instructions Error status example Preventative measures 2 cases Do not use input...

Page 311: ...you have to copy the input port as internal paramet er or carry bit and then use compare jump instruction bit tt while 1 tt P00 if tt 0 P10 1 else P10 0 P11 1 zzz MOV C 080 0 input port use internal...

Page 312: ...visit Zilog s Technical Support page at http support zilog com To learn more about this product find additional documentation or to discover other fac ets about Zilog product offerings please visit th...

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