30
Chapter 4
BIOS Setup
Delayed Transaction
When enabled, the south bridge ICH2 will supports the Delayed
Transaction mechanism when it is the target of a PCI transaction.
[Enable(
Default Value
),Disabled]
AGP Aperture Size (MB)
This field configures the main memory size for AGP graphics data
used.
[4MB, 8MB, 16MB, 32MB,64MB(
Default Value
), 128MB, 256MB]
DRAM RAS# Precharge
If an insufficient number of cycles is allowed for the RAS to
accumulate its charge before DRAM refresh, the refresh may be
incomplete and the DRAM may fail to retain data. This controls the
idle(delay) clocks after issueing a prechange command to the
SDRAM.
[2,3(
Default Value
)]
System BIOS Cacheable
When enabled, accesses to the system BIOS will be cached.
[Enable(
Default Value
),Disabled]
Video BIOS Cacheable
When enabled, access to the video BIOS will be cached.
[Enable, Disabled(
Default Value
)]
Video RAM Cacheable
When Disabled, access to the video memory located at A0000H to
BFFFFH will be cached.
[Enabled, Disabled (
Default Value
)]
DRAM RAS# to CAS# Delay
This controls the number of clocks between the SDRAM active
command and the read / write command.
[2,3(
Default Value
)]
