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iWave iW-RainboW-G21M, Hardware User'S Manual

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iWave iW-RainboW-G21M Hardware User'S Manual Download Page 40

 

 

REL1.1 

Page 40 of 92 

RZ/G1H Qseven SOM Hardware User Guide

 

iWave Systems Technologies Pvt. Ltd. 

194 

SPKR/ 
GP_PWM_O
UT2 

TPU0TO0/MD24
(GP0_20)

 ¹

 

A4/MD24/ 
AL6 

O, 3.3V CMOS/ 
100K PU 

General  purpose  Pulse  width 
modulation. 

Note:  TPU0TO0  is  connected  to 
this  pin  for  implementing  PWM 
through  resistor  and  default 
populated. 
Note:  Same  signal  is  also 
connected 

to 

Expansion 

connector2 37

th

 Pin.

 

195 

FAN_TACHOI
N/GP_TIMER
_IN 

NC 

NA 

- 

NC. 

196 

FAN_PWMO
UT/GP_PWM
_OUT1 

TPU0TO1/MD23
(GP0_21)

 ¹

 

A5/MD23/ 
AH5 
 

O, 3.3V CMOS/ 
100K PU 

General  purpose  Pulse  width 
modulation. 

Note:  TPU0TO1  is  connected  to 
this  pin  for  implementing  PWM 
through  resistor  and  default 
populated. 
Note:  Same  signal  is  also 
connected 

to 

Expansion 

connector2 29

th

 Pin.

 

197 

GND 

GND 

NA 

Power 

Ground. 

198 

GND 

GND 

NA 

Power 

Ground. 

199 

SPI_MOSI 

MSIOF0_TXD/M
DT1(GP5_15)

 ¹

 

MSIOF0_TXD/MDT
1/W29 

O, 3.3V CMOS/ 
10K PD 

SPI  Master  serial  output/Slave 
serial input (MSIOF0). 

200 

SPI_CS0# 

MSIOF0_SYNC(
GP5_13) 

MSIOF0_SYNC/ 
V25 

O, 3.3V CMOS 

SPI  frame  synchronization  signal 
(MSIOF0). 

Note:  Same  signal  is  optionally 
connected 

to 

Qseven 

edge 

connector  154

th

  pin  through 

resistor 

and 

default 

not 

populated.

 

201 

SPI_MISO 

MSIOF0_RXD(G
P5_17) 

MSIOF0_RXD/ 
W27 

I, 3.3V CMOS 

SPI Master serial input/Slave serial 
output (MSIOF0). 

202 

SPI_CS1# 

MSIOF0_SS1/M
D0(GP5_14) 

¹

 

MSIOF0_SS1/MD0/ 
W28 

O, 3.3V CMOS/ 
10K PD 

SPI frame synchronization signal1 
(MSIOF0). 

203 

SPI_SCK 

MSIOF0_SCK(GP
5_12) 

MSIOF0_SCK/ 
Y31 

O, 3.3V CMOS 

SPI Serial clock (MSIOF0). 

204 

MFG_NC4 

JTAG_TRSTB 

NA 

- 

Default NC. 

Note: Optionally CPU TRST# pin is 
connected to this pin through 1.8V 
to  3.3V  level  translator  and 
default not populated. 

205 

VCC_5V_SB 

NC 

NA 

- 

NC. 

Summary of Contents for iW-RainboW-G21M

Page 1: ...REL1 1 Page 1 of 92 RZ G1H Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd iW RainboW G21M RZ G1H Qseven SOM Hardware User Guide ...

Page 2: ...t the document PROPRIETARY NOTICE This document contains proprietary material for the sole use of the intended recipient s Do not read this document if you are not the intended recipient Any review use distribution or disclosure by others is strictly prohibited If you are not the intended recipient or authorized to receive for the recipient you are hereby notified that any disclosure copying distr...

Page 3: ...rrata and associated issues Trademarks All registered trademarks product names mentioned in this publication are the property of their respective owners and used for identification purposes only Certification iWave Systems Technologies Pvt Ltd is an ISO 9001 2015 Certified Company Warranty RMA Warranty support for Hardware 1 Year from iWave or iWave s EMS partner For warranty terms go through the ...

Page 4: ...2 6 1 Gigabit Ethernet 19 2 6 2 USB 3 0 Host Interface 20 2 6 3 PCIe Interface 20 2 6 4 SATA Interface Optional 21 2 6 5 USB 2 0 OTG Interface 21 2 6 6 USB 2 0 Host Interface 21 2 6 7 SD Interface 22 2 6 8 LVDS Display Interface 22 2 6 9 HDMI Interface Optional 23 2 6 10 I2S Audio Interface 23 2 6 11 DATA UART Interface 24 2 6 12 CAN Interface 24 2 6 13 SPI Interface 24 2 6 14 I2C Interface 25 2 6...

Page 5: ...CAL SPECIFICATION 79 3 1 Electrical Characteristics 79 3 1 1 Power Input Requirement 79 3 1 2 Power Input Sequencing 80 3 1 3 Power Consumption 81 3 2 Environmental Characteristics 82 3 2 1 Environmental Specification 82 3 2 2 Heat Sink Spreader 82 3 2 3 RoHS Compliance 84 3 2 4 Electrostatic Discharge 84 3 3 Mechanical Characteristics 85 3 3 1 Qseven SOM Mechanical Dimensions 85 3 3 2 Guidelines ...

Page 6: ...1H SPI Programming Board 90 Figure 18 RZ G1H Qseven SOM Development Platform with Add on Module 91 List of Tables Table 1 Acronyms Abbreviations 7 Table 2 Terminology 9 Table 3 Compatible Magnetics 19 Table 4 Qseven PCB Edge Connector Pin Assignment 27 Table 5 Parallel Camera Interface Pin Assignment on Expansion connector1 43 Table 6 Expansion Connector1 Pin Assignment 44 Table 7 Compatible Magne...

Page 7: ...r of 70mm x 70mm and have specified pin outs based on the high speed MXM system connector that has a standardized pin out regardless of the vendor A single ruggedized MXM connector provides the carrier board interface to carry all the I O signals to and from the Qseven module 1 3 List of Acronyms The following acronyms will be used throughout this document Table 1 Acronyms Abbreviations Acronyms A...

Page 8: ...B Printed Circuit Board PCIe Peripheral Component Interconnect Express PTH Plated Through hole PWM Pulse Width Modulation QSPI Quad Serial Peripheral Interface RoHS Restriction on Hazardous Substances RTC Real Time Clock SATA Serial Advanced Technology Attachment SCIF Serial Communication Interface with FIFO SD Secure Digital SDHI SD Card Host Interface SSI Serial Sound Interface SDRAM Synchronous...

Page 9: ...Signal CMOS Complementary Metal Oxide Semiconductor Signal DIFF Differential Signal LVDS Low Voltage Differential Signal OD Open Drain Signal OC Open Collector Signal Power Power Pin PU Pull Up PD Pull Down NA Not Applicable NC Not Connected Note Signal Type does not include internal pull ups or pull downs implemented by the chip vendors and only includes the pull ups or pull downs implemented On ...

Page 10: ...l CAN0_RX is the functionality which we are using and GP4_26 is the GPIO number If CPU pin has multiplexing option and selected as GPIO function then the signal name is mentioned as GPIO_Functionality Description GPIO Number Example GPIO_PCIe_RST MD4 GP4_31 In this signal PCIe_RST is the GPIO functionality which we are using and GP4_31 is the GPIO number If CPU pin doesn t have multiplexing option...

Page 11: ...ptional Expansion Connector2 80Pin header CAN0 CAN x 1 DDR3 1GB Upgradable DDR3 32bit DBSC3 CH1 PWM x 2 TPU0TO0 TPU0TO1 UART with CTS RTS x 1 SCIFB1 SATA0 SATA1 is not supported by default VI2 camera interface supports only Embedded Sync Through DIP switch either MMC1 8bit Since MMC_DATA7 line is shared with VI1_CLK or VI1 can be selected at a time If VI1 is used in 16bit then VI2 cannot be used 4...

Page 12: ...Gigabit Ethernet PHY Transceiver 10 100 Ethernet PHY Transceiver USB 2 0 High Speed 2 Port Hub RTC controller SPI Programming Header JTAG Header Optional HDMI Transmitter Optional Qseven PCB Edge Interfaces Gigabit Ethernet x 1 Port through On SOM Gigabit Ethernet PHY transceiver 3 USB 3 0 Host x 1 Port 4 PCIe x 1 Port5 SATA x 1 Port Optional 4 5 USB 2 0 OTG x 1 Port USB 2 0 Host x 1 Ports USB 2 0...

Page 13: ...al Specification Power Supply 5V 2A Power IN connector for Standalone usage Optional Form Factor 70mm x 70mm 1 In RZ G1H CPU SPI and VIN2 signals are multiplexed in same pins and so either one interface only can be used at a time 2 In RZ G1H CPU eMMC Data7 and VIN1 clock is multiplexed in same pin and so eMMC will operate only in 4bit mode when VIN1 is supported If VIN1 is not supported then eMMC ...

Page 14: ... G1H CPU s DU_LVDS1 output can be connected to either HDMI transmitter or Secondary LVDS port of Qseven Edge By default it is connected to Secondary LVDS port of Qseven Edge 7 In RZ G1H CPU VIN0 2nd 8bit and VIN3 are multiplexed in same pins and so VIN3 cannot be supported when VIN0 is supported in 16bit mode If VIN0 is supported in 8bit mode then VIN3 also can be supported in 8bit mode 8 In RZ G1...

Page 15: ...Microprocessor core and Quad ARM Cortex A7 Microprocessor core both can operate up to 1 4 GHz core and 780MHz core respectively The Block Diagram of RZ G1H CPU from the datasheet is shown below for reference Figure 2 RZ G1H CPU Simplified Block Diagram Note Please refer the latest RZ G1H Datasheet Reference Manual for Electrical characteristics of RZ G1H CPU which may be revised from time to time ...

Page 16: ... program The SPI flash memory U21 is physically located on top side of the Qseven SOM In RZ G1H CPU QSPI and VIN2 are multiplexed in same pins and so either one interface only can be used at a time A bus switch is provided in these pins to select between QSPI and VIN2 This bus switch can be controlled by software though GPIO pin GP0_18 If GP0_18 pin is set to low then QSPI is selected If GP0_18 pi...

Page 17: ...hich is controlled by a DIP switch SW3 to select between eMMC 8bit and VIN1 If the DIP switch is set to OFF position then eMMC will work in 8bit mode and VIN1 cannot be supported If the DIP switch is set to ON position then VIN1 can be supported and eMMC will work only in 4bit mode This DIP switch position can be read by software though GPIO pin GP4_12 Note For more details on DIP switch SW3 refer...

Page 18: ... per Qseven Specification 2 0 The interfaces which are available at 230pin Qseven Edge connector are explained in the following sections Figure 3 Qseven PCB Edge Connector Number of Pins 230 Connector Part Not Applicable On Board PCB Edge connector Mating Connector IMSA 18010S 230A GN1 from IRISO 88882 2D0K from Aces AS0B326 S78N 7F from FOXCONN CN113 230 0001VE from Yamaichi Electronics ...

Page 19: ...HY has on chip termination on differential pairs and so no need to add any termination externally The below table provides some of the compatible magnetics recommended by the PHY Manufacturer Table 3 Compatible Magnetics Part Description Part Number Manufacturer Temperature Gigabit Ethernet Discrete Transformer TG1G E001NZRL HALO 40 C to 85 C Gigabit Ethernet Discrete Transformer HX5008NL Pulse 40...

Page 20: ...a time By default USB3 0 is supported Please contact iWave if SATA support is required 2 6 3 PCIe Interface The RZ G1H Qseven SOM supports one PCI Express Gen2 0 lane on Qseven Edge connector RZ G1H CPU s PCIEC module with integrated PHY is used for PCIe Interface which can support PCIe Gen2 0 at multiple speeds 2 5GT s and 5GT s RZ G1H CPU s PCIe PHY output is connected to Qseven Edge connector P...

Page 21: ... 5Mbps transfer RZ G1H CPU s USB0 OTG controller can operate in Host or Function Peripheral mode The RZ G1H CPU s USB0 PHY output is directly connected to Qseven Edge connector USB Port1 Also USB VBUS USB ID input from Qseven Edge connector is connected to RZ G1H CPU s VBUS GPIO GP5_20 pins correspondingly USB_DRIVE_VBUS to Qseven Edge connector is connected from RZ G1H CPU s USB0_PWEN pin for con...

Page 22: ... can be connected to either LVDS or RGB interface The RZ G1H Qseven SOM supports two LVDS interface on Qseven Edge connector The RZ G1H CPU s DU_LVDS0 and DU_LVDS1 output is directly connected to primary LVDS and secondary LVDS of Qseven Edge connector The RZ G1H CPU s LVDS output supports five differential output pairs 4 data and 1 clock that conform to the TIA EIA 644 standard with dot clock ope...

Page 23: ...n Edge connector pins 131 133 137 139 143 145 149 150 151 152 153 on Table 4 Note In RZ G1H SOM RZ G1H CPU s DU_LVDS1 output can be connected to either HDMI transmitter or Secondary LVDS port of Qseven Edge By default it is connected to Secondary LVDS port of Qseven Edge Please contact iWave for more details Important Note To support this HDMI feature customer must be having HDMI Adopter HDCP Lice...

Page 24: ... more CAN interface on Expansion connector2 RZ G1H CPU s CAN module supports two channels in which CAN1 channel is connected to Qseven Edge connector The RZ G1H CPU s CAN module complies with the ISO11898 1 Specifications and supports programmable bit rate up to 1 Mbps with both formats of messages namely the standard identifier 11 bits and extended ID 29 bits It also supports 64 mailboxes in two ...

Page 25: ...ce on Qseven Edge connector RZ G1H CPU s TPU0 Time Pulse Unit is used for PWM interface RZ G1H CPU s TPU0 supports upto four channels in which TPU0TO0 TPU0TO1 TPU0TO2 channels are used in PWM mode on Qseven Edge connector TPU0 in PWM mode allows the output of a PWM waveform with any duty cycle range from 0 to 100 For more details refer Qseven Edge connector pins 123 194 196 on Table 4 2 6 16 GPIO ...

Page 26: ... and generates all other required powers internally On SOM itself RZ G1H Qseven SOM also uses VCC_RTC coin cell power input from Qseven Edge connector to RTC controller for real time clock when VCC is off RZ G1H Qseven SOM doesn t use Standby power supply from Qseven Edge connector For more details refer Qseven Edge connector pins 193 211 to 230 on Table 4 Note The RZ G1H Qseven SOM can also be po...

Page 27: ...13th pins through resistors and default populated So use only in one place 8 GBE_LINK10 00 GPHY_LINK_LED 2 NA O 3 3V CMOS 4 7K PD Gigabit Ethernet link status LED Note Same signal is also connected to Qseven edge connector 7th 13th pins through resistors and default populated So use only in one place 9 GBE_MDI1 GPHY_BTXRXM NA IO DIFF Gigabit Ethernet MDI differential pair 1 negative 10 GBE_MDI0 GP...

Page 28: ... 22 LID_BTN NC NA NC 23 GND GND NA Power Ground 24 GND GND NA Power Ground 25 GND GND NA Power Ground 26 PWGIN PWRGIN NA I 5V CMOS Active high enable signal for SOM Power Note For more details on PWRGIN refer Section 2 6 19 3 1 2 27 BATLOW NC NA NC 28 RSTBTN RSTBN NA I 3 3V CMOS 10K PU Active low reset button input 29 SATA0_TX NC NA Default NC Note TODP0_SATA TODP1_SATA is optionally connected to ...

Page 29: ...SATA1_RX NC NA NC 37 SATA0_RX NC NA Default NC Note RIDN0_SATA RIDN1_SATA is optionally connected to this pin for SATA0_RXN through 0 01uF AC Coupling Capacitor and default not populated 38 SATA1_RX NC NA NC 39 GND GND NA Power Ground 40 GND GND NA Power Ground 41 BIOS_DISABL E BOOT_ALT NC NA NC 42 SDIO_CLK SD2_CLK GP3_1 6 SD2_CLK R1 O 3 3V CMOS 1K PU SD2 clock 43 SDIO_CD SD2_CD GP3_22 SD2_CD T2 I...

Page 30: ...rol output for USB port1 VBUS 57 GND GND NA Power Ground 58 GND GND NA Power Ground 59 HDA_SYNC I2S_WS SSI_WS34 GP4_ 9 SSI_WS34 R28 O 3 3V CMOS SSI3 4 Audio transmit frame synchronization 60 SMB_CLK GP1_I2C_CLK I2C0_SCL IIC0_SCL AG15 O 3 3V OD 1K PU I2C0 clock Note Same signal is also connected to On SOM RTC controller 61 HDA_RST I2S_RST GPIO_SSI_RST G P1_29 DACK2 AD6 O 3 3V CMOS Audio codec reset...

Page 31: ...SI_SCK4 T31 O 3 3V CMOS 10K PU Thermal Trip Note GP4_11 is connected to this pin as GPIO for implementing Thermal Trip 72 WDOUT NC NA NC 73 GND GND NA Power Ground 74 GND GND NA Power Ground 75 USB_P7 USB_SSTX0 USB3_TXN TODN0_SATA AL30 O DIFF 0 1uF AC coupled USB3 0 transmit data output negative 76 USB_P6 USB_SSRX0 USB3_RXN RIDN0_SATA AL28 I DIFF USB3 0 receive data input negative 77 USB_P7 USB_SS...

Page 32: ... USBDM_DN2 pin 88 USB_P2 USB2_DM USB2_DM AJ31 IO DIFF USB Host Port2 data negative Note This pin is connected from CPU USB2_DM pin 89 USB_P3 USB_HUB2OUT _DP NA IO DIFF USB Host port3 data positive Note This pin is connected from On SOM USB Hub USBDP_DN2 pin 90 USB_P2 USB2_DP USB2_DP AK31 IO DIFF USB Host Port2 data positive Note This pin is connected from CPU USB2_DP pin 91 USB_VBUS VCC_VBUS NA I ...

Page 33: ...J22 O 1 8V LVDS LVDS secondary channel differential pair0 negative Note If HDMI transmitter is supported on SOM then this pin will become NC 103 eDP0_TX1 LVDS_A1 DU_LVDS0_CH1 _P DU_LVDS0_CH1_P AG19 O 1 8V LVDS LVDS primary channel differential pair1 positive 104 eDP1_TX1 LVDS_B1 LVDS1_CH1_P DU_LVDS1_CH1_P AL21 O 1 8V LVDS LVDS secondary channel differential pair1 positive Note If HDMI transmitter ...

Page 34: ...P AJ17 O 1 8V LVDS LVDS primary channel differential pair3 positive 114 eDP1_TX3 LVDS_B3 LVDS1_CH3_P DU_LVDS1_CH3_P AG22 O 1 8V LVDS LVDS secondary channel differential pair3 positive Note If HDMI transmitter is supported on SOM then this pin will become NC 115 eDP0_TX3 LVDS_A3 DU_LVDS0_CH3 _N DU_LVDS0_CH3_N AJ16 O 1 8V LVDS LVDS primary channel differential pair3 negative 116 eDP1_TX3 LVDS_B3 LVD...

Page 35: ...s also connected to Expansion connector2 36th Pin 124 GP_1 Wire_Bus NC NA NC 125 GP2_I2C_DA T LVDS_DID_ DAT I2C3_SDA IIC3_SDA AH15 IO 3 3V OD 1K PU I2C3 data Note Same signal is optionally connected to Qseven edge connector 126th pin through resistor and default not populated 126 eDP0_HPD LVDS_BLC_ DAT NC NA Default NC Note I2C3_SDA is optionally connected to this pin through resistor and default ...

Page 36: ...MI differential clock positive HDMI_CLKP signal from HDMI Transmitter is Optionally connected to this pin 132 RSVD NC NA NC 133 DP_LANE3 TMDS_CLK NC NA Default NC Note HDMI differential clock negative HDMI_CLKM signal from HDMI Transmitter is optionally connected to this pin 134 RSVD NC NA NC 135 GND GND NA Power Ground 136 GND GND NA Power Ground 137 DP_LANE1 TMDS_LANE 1 NC NA Default NC Note HDM...

Page 37: ..._LANE0 TMDS_LANE 2 NC NA Default NC Note HDMI differential data lane 2 positive HDMI_D2P signal from HDMI Transmitter is optionally connected to this pin 150 HDMI_CTRL_ DAT NC NA Default NC Note HDMI I2C data HDMI_I2C_DAT signal from HDMI Transmitter is optionally connected to this pin 151 DP_LANE0 TMDS_LANE 2 NC NA Default NC Note HDMI differential data lane 2 negative HDMI_D2M signal from HDMI T...

Page 38: ...connector 33rd pin through resistor and default not populated 157 PCIE_CLK_RE F PCIe_REFCLK_D N NA O DIFF PCIe differential reference clock negative from 100Mhz oscillator 158 PCIE_RST GPIO_PCIe_RST MD4 GP4_31 MD4 MSIOF3_SS1 Y29 O 3 3V CMOS 100K PU PCIe reset Note GP4_31 is connected to this pin as GPIO for implementing PCIe reset Note Same signal is optionally connected to Expansion connector2 57...

Page 39: ...uF AC coupled PCIe Transmit data output negative 182 PCIE0_RX PCIe1_RXN RIDN1_SATA AL24 I DIFF PCIe Receive data input negative 183 GND GND NA Power Ground 184 GND GND NA Power Ground 185 LPC_AD0 GPIO0 Q7_GPIO0_ GP0 _24 A8 AL5 IO 3 3V CMOS General purpose input output 0 186 LPC_AD1 GPIO1 Q7_GPIO1_ GP0 _25 A9 AJ4 IO 3 3V CMOS General purpose input output 1 187 LPC_AD2 GPIO2 Q7_GPIO2_ GP0 _26 A10 AK...

Page 40: ...th Pin 197 GND GND NA Power Ground 198 GND GND NA Power Ground 199 SPI_MOSI MSIOF0_TXD M DT1 GP5_15 MSIOF0_TXD MDT 1 W29 O 3 3V CMOS 10K PD SPI Master serial output Slave serial input MSIOF0 200 SPI_CS0 MSIOF0_SYNC GP5_13 MSIOF0_SYNC V25 O 3 3V CMOS SPI frame synchronization signal MSIOF0 Note Same signal is optionally connected to Qseven edge connector 154th pin through resistor and default not p...

Page 41: ...or and default not populated 210 MFG_NC3 JTAG_TMS TMS AF14 IO 3 3V CMOS CPU TMS pin is connected to this pin through 1 8V to 3 3V level translator and default populated 211 VCC VCC_5V NA I 5V Power Supply Voltage 212 VCC VCC_5V NA I 5V Power Supply Voltage 213 VCC VCC_5V NA I 5V Power Supply Voltage 214 VCC VCC_5V NA I 5V Power Supply Voltage 215 VCC VCC_5V NA I 5V Power Supply Voltage 216 VCC VCC...

Page 42: ...ll effort has been made in RZ G1H Qseven SOM design to provide maximum interfaces of RZ G1H CPU to the carrier board by adding two 80Pin Expansion connectors The interfaces which are available at 80pin Expansion Connector1 are explained in following sections Figure 4 Expansion Connector1 Number of Pins 80 Connector Part Number DF17 2 0 80DP 0 5V 57 Mating Connector DF17 3 0 80DS 0 5V 57 from Hiros...

Page 43: ... 8bit 4 6 8 10 48 68 70 71 73 74 75 76 79 16bit 4 6 8 10 25 43 46 48 53 55 57 68 70 71 72 73 74 75 76 78 79 VIN1 8bit 34 36 38 40 42 50 52 54 56 58 60 64 66 16bit 3 7 18 20 22 24 34 36 38 40 42 50 52 54 56 58 60 63 64 66 67 VIN2 8bit 3 7 9 11 13 15 17 19 21 61 VIN3 8bit 24 25 27 35 45 47 49 51 53 55 57 63 67 Note In RZ G1H CPU either four 8bit camera can be supported at a time VI0 8bit VI1 8bit VI...

Page 44: ... Channel1 green data bit6 GroupB in 16bit mode 4 VI0_DATA6 VI0_B6 GP2_7 2 VI0_DATA6 VI0_B6 AA6 I 3 3V CMOS Video Input Channel0 data bit6 in 8bit mode or Video Input Channel0 blue data bit6 in 16bit mode 5 GND NA Power Ground 6 VI0_DATA0 VI0_B0 GP2_1 2 VI0_DATA0 VI0_B0 Y6 I 3 3V CMOS Video Input Channel0 data bit0 in 8bit mode or Video Input Channel0 blue data bit0 in 16bit mode 7 VI2_G7 QSPI_IO2 ...

Page 45: ...el1 green data bit3 GroupB in 16bit mode 19 VI2_G1 GP0_28 A12 AK3 I 3 3V CMOS Video Input Channel2 green data bit1 in 8bit mode 20 VI1_G5 GP1_12 EX_CS0 AC1 I 3 3V CMOS Video Input Channel1 green data bit5 GroupB in 16bit mode 21 VI2_G0 GP0_27 A11 AL4 I 3 3V CMOS Video Input Channel2 green data bit0 in 8bit mode 22 VI1_G4 GP1_22 WE1 AH2 I 3 3V CMOS Video Input Channel1 green data bit4 GroupB in 16b...

Page 46: ... mode 36 VI1_CLKENB GP1_26 DREQ1 AD5 I 3 3V CMOS Video Input Channel1 clock enable GroupB 37 GPIO MD16 GP1_19 RD AD3 IO 3 3V CMOS 100K PU General Purpose Input Output 38 VI1_VSYNC GP1_25 DACK0 AC6 I 3 3V CMOS Video Input Channel1 Vertical synchronize signal GroupB 39 GPIO MD13 GP1_18 BS AE5 IO 3 3V CMOS 100K PU General Purpose Input Output 40 VI1_HSYNC GP1_24 DREQ0 AC5 I 3 3V CMOS Video Input Chan...

Page 47: ...l1 data bit6 GroupB in 8bit mode or Video Input Channel1 blue data bit6 GroupB in 16bit mode 53 VI3_DATA3 VI0_G7 GP0_3 D3 AJ9 I 3 3V CMOS Video Input Channel3 data bit3 in 8bit mode or Video Input Channel0 green data bit7 in 16bit mode 54 VI1_B5 VI1_DATA5 GP3_5 SD0_DAT3 V5 I 3 3V CMOS Video Input Channel1 data bit5 GroupB in 8bit mode or Video Input Channel1 blue data bit5 GroupB in 16bit mode 55 ...

Page 48: ... 16bit mode 65 GPIO_EXP GP1_21 WE0 AH1 IO 3 3V CMOS General purpose input output 66 VI1_B0 VI1_DATA0 GP3_0 SD0_CLK V1 I 3 3V CMOS Video Input Channel1 data bit0 GroupB in 8bit mode or Video Input Channel1 blue data bit0 GroupB in 16bit mode 67 VI3_VSYNC VI1_G2 GP1_1 7 EX_CS5 AE4 I 3 3V CMOS Video Input Channel3 Vertical synchronize signal in 8bit mode or Video Input Channel1 green data bit2 GroupB...

Page 49: ...LD GP0_15 2 D15 AK7 I 3 3V CMOS Video Input Channel0 Field 77 GND NA Power Ground 78 VI0_G3 GP0_11 2 D11 AL8 I 3 3V CMOS Video Input Channel0 green data bit3 in 16bit mode 79 VI0_DATA7 VI0_B7 GP2_8 2 VI0_DATA7 VI0_B7 AA5 I 3 3V CMOS Video Input Channel0 data bit7 in 8bit mode or Video Input Channel0 blue data bit7 in 16bit mode 80 GND NA Power Ground Important Note These signals are also used for ...

Page 50: ... SOM supports Expansion connector2 also to pull out more interfaces of RZ G1H CPU The interfaces which are available at 80pin Expansion connector2 are explained in the following sections Figure 5 Expansion Connector2 Number of Pins 80 Connector Part Number DF17 2 0 80DP 0 5V 57 Mating Connector DF17 3 0 80DS 0 5V 57 from Hirose Staking Height 5mm ...

Page 51: ...acturer Temperature RJ45 Magjack with Green Orange LED s 0821 1X1T 36 F Bel Fuse 40 C to 85 C RJ45 Magjack with Green Yellow LED s SI 46001 F Bel Fuse 40 C to 85 C RJ45 Magjack with Green Yellow LED s HFJ11 E2450E L12RL Halo Electronics 40 C to 85 C RJ45 Magjack with Green Yellow LED s JX0011D21BNL Pulse Electronics 40 C to 85 C For more details refer Expansion connector2 pins 2 4 8 10 11 12 14 on...

Page 52: ... for the receive FIFO register enabling fast for efficient and continuous communications The RZ G1H CPU s HSCIF0 is a high speed serial communication interface with built in FIFO buffers that handles asynchronous communication It has two 128 stage FIFO buffers separately for transmission and reception which enables fast efficient and uninterrupted communication For more details refer Expansion con...

Page 53: ... refer Expansion connector2 pins 61 63 65 67 69 on Table 8 2 8 6 PWM Interface The RZ G1H Qseven SOM supports three PWM interface on Expansion Connector2 RZ G1H CPU s PWM0 PWM3 and PWM4 channels are used for PWM interface This PWM timer has a 10 bit counter and supports configurable PWM output cycle within the range from 2 cycles to 224 1024 cycles of internal bus clock i e from 30 77 ns to 264 se...

Page 54: ...TH_TX_EN MD11 GP2_26 from EtherMAC is optionally connected to this pin through resistor and default not populated 5 NC NA NC 6 GND NA Power Ground 7 NC NA NC 8 ETH_RXP NA I DIFF 10 100Mbps Ethernet Receiver pair positive Note ETH_RXD0 GP2_20 from EtherMAC is optionally connected to this pin through resistor and default not populated 9 NC NA NC 10 ETH_RXM NA I DIFF 10 100Mbps Ethernet Receiver pair...

Page 55: ...r and default not populated 18 ETH_MAGIC MD10 GP2_2 7 ETH_MAGIC AF10 O 3 3V CMOS 10K PD ETH_MAGIC from EtherMAC is connected to this pin 19 ETH_TXD0 MD9 GP2_28 ETH_TXD0 AE10 O 3 3V CMOS 10K PU Default NC Note ETH_TXD0 from EtherMAC is optionally connected to this pin through resistor and default not populated 20 SCIFB1_RXD GP4_15 SSI_WS5 U30 I 3 3V CMOS Serial Communication Interface SCIFB1 Serial...

Page 56: ...ose input output 32 GPIO MD18 GP1_0 A16 MD18 AG1 IO 3 3V CMOS 10K PD General purpose input output 33 GND NA Power Ground 34 GND NA Power Ground 35 GPIO MD25 GP0_19 A3 MD25 AJ6 IO 3 3V CMOS 10K PD General purpose input output 36 TPU0TO2 MD22 GP0_22 A6 MD22 AJ5 O 3 3V CMOS 100K PU This pin is connected to TPU0TO2 for implementing PWM output Note Same signal is also connected to Qseven Edge connector...

Page 57: ...his pin through resistor and default populated Note Same signal is optionally connected to On SOM HDMI Transmitter through resistor and default not populated 51 HSCIF0_HCTS0 GP5_10 HCTS0 U26 IO 3 3V CMOS High Speed Serial Communication Interface HSCIF0 Clear to Send 52 SSI_WS0129 GP4_4 SSI_WS0129 P30 O 3 3V CMOS Audio Word select for SSI channel 0 SSI_WS0129 is connected to this pin through resist...

Page 58: ...urpose input output 61 MSIOF3_SS2 GP4_27 SCIFA0_SCK AA30 O 3 3V CMOS SPI chip select 2 MSIOF3 62 HSCIF0_HTX0 MD1 GP5_9 HTX0 MD1 V27 O 3 3V CMOS 10K PD High Speed Serial Communication Interface HSCIF0 Serial Data Transmitter 63 MSIOF3_TXD MD2 GP5_3 SCIFA1_RTS MD2 Y26 O 3 3V CMOS 100K PU SPI transmit data output MSIOF3 64 HSCIF0_HRX0 GP5_8 HRX0 V26 I 3 3V CMOS High Speed Serial Communication Interfa...

Page 59: ...r and default not populated 75 GND NA Power Ground 76 GND NA Power Ground 77 SCIF0_TX0 MD5 GP4_29 SCIFA0_TXD MD5 Y30 O 3 3V CMOS 100K PU Serial Communication Interface SCIF0 Serial Data Transmitter 78 DU_DOTCLKIN1 DU_DOTCLKIN1 Ah13 I 3 3V CMOS DU0 dot clock input is connected to this pin through resistor and default populated Note MLBP_DAT_P is optionally connected to this pin through resistor and...

Page 60: ...ysical dimension of connector is made smaller in RZ G1H Qseven SOM because of space constraint RZ G1H CPU s JTAG pins are 1 8V tolerant and so 1 8V reference power is provided to pin 1 of the connector to allow JTAG tool to automatically configure the logic signals for the right voltage JTAG connector J3 is physically located on topside of the SOM This is optional feature and may not be populated ...

Page 61: ...a input 6 GND Power Ground 7 TMS IO 1 8V CMOS 4 7K PU JTAG test mode select 8 GND Power Ground 9 TCK I 1 8V CMOS 4 7K PU JTAG test Clock 10 GND Power Ground 11 I 1 8V CMOS 10K PD Only pull down is provided 12 GND Power Ground 13 TDO O 1 8V CMOS JTAG test data output 14 GND Power Ground 15 RESET I 1 8V CMOS 4 7K PU Reset input 16 GND Power Ground 17 I 1 8V CMOS 10K PU Only pull up is provided 18 GN...

Page 62: ... physically located on top side of the SOM as shown below Number of Pins 6 Connector Part Number TMM 103 01 L D Mating Connector M22 6340342 from Harwin Inc Important Note Never connect the external SPI programmer to RZ G1H Qseven SOM when SOM power is ON Figure 7 SPI Programming Header Table 10 SPI Programming Header Pin Assignment Pin No Signal Name Signal Type Termination Description 1 SPI_MISO...

Page 63: ... P1 for standalone purpose This is the optional feature and not populated by default Figure 8 2Pin Power Connector Table 11 Power IN Connector BOM Sl No Part Description Part Number Identifier1 Package Quantity 1 CONN HEADER VERT 2CKT 2 5MM 0099990986 P1 2Pin TH 1 2 FUSE FAST 24VDC 3A SF 0603F300 2 F1 0603 1 3 CONN HOUSING 2POS 2 5MM SHROUD 0050375023 Mating connector for P1 NA 1 4 CONN FEMALE 22 ...

Page 64: ... 12 RZ G1H CPU IOMUX for Qseven Edge Connector interfaces Interface Function Qseven Edge Pin Number RZ G1H CPU Pin Number Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9 Function 10 GPIO Default State SD2 42 R1 SD2_CLK MMC0_CLK VI0_DATA0_ B VI0_B0_B VI3_DATA0_ B GP3_16 GP3_16 45 T4 SD2_CMD MMC0_CMD VI0_DATA1_ B VI0_B1_B SCIFB1_SCK_E SCK1_D VI3_DAT...

Page 65: ..._USB3 75 AL30 TODN0_SATA TODN0_USB3 TODN0_USB3 USB 2 0 95 AF31 USB0_DP USB0_DP 93 AE31 USB0_DM USB0_DM 88 AJ31 USB2_DM USB2_DM 90 AK31 USB2_DP USB2_DP 56 AC28 USB0_PWEN GP5_18 GP5_18 92 AC29 USB1_PWEN AUDIO_CLKO UT_D GP5_20 GP5_20 79 AC30 USB2_OVC GP5_23 USB2_OVC I2C 60 AG15 IIC0_SCL I2C0_SCL IIC0_SCL 62 AF15 IIC0_SDA I2C0_SDA IIC0_SDA 66 AB31 IIC2_SCL_B I2C2_SCL_B GP4_0 GP4_0 68 AC31 SCIFB1_RXD_ ...

Page 66: ..._LVDS0_C H2_N DU_LVDS0_C H2_N 113 AJ17 DU_LVDS0_C H3_P DU_LVDS0_C H3_P 115 AJ16 DU_LVDS0_C H3_N DU_LVDS0_C H3_N 112 U4 SD1_DAT1 AVB_LINK SCIFB0_TXD _B GP3_11 GP3_11 111 AJ12 DU_DOTCLKI N2 GP5_28 GP5_28 36 AJ5 A6 SCIFA1_RTS _ B TPU0TO2 GP0_22 GP0_22 LVDS1 120 AL19 DU_LVDS1_CL K_P DU_LVDS1_CL K_P 122 AL20 DU_LVDS1_CL K_N DU_LVDS1_CL K_N 100 AJ23 DU_LVDS1_C H0_P DU_LVDS1_C H0_P 102 AJ22 DU_LVDS1_C H0...

Page 67: ...TA7 _B GP4_22 GP4_22 171 T28 SSI_SDATA8 SCIFB2_TXD CAN0_TX_C SSI_SDATA8 _B GP4_23 GP4_23 PCIe 179 AL25 TODP1_SATA TODP1_PCIe TODP1_PCIe 181 AL26 TODN1_SATA TODN1_PCIe TODN1_ PCIe 156 AB4 VI1_DATA4 VI 1_B4 SCIFA1_RTS _ D AVB_MAGIC GP2_14 GP2_14 158 Y29 SCIFA0_RTS HRTS1 RTS0 MSIOF3_SS 1 DU_DG0 PWM1_B GP4_31 GP4_31 180 AL23 RIDP1_SATA RIDP1_PCIe RIDP1_PCIe 182 AL24 RIDN1_SATA RIDN1_PCIe RIDN1_PCIe GP...

Page 68: ... 200 V25 MSIOF0_SYNC SSI_SCK2 DU_DB7 HRX0_C GP5_13 GP5_13 201 W27 MSIOF0_RXD SSI_WS2 DU_CDE SCIFA2_RXD _B GP5_17 GP5_17 202 W28 MSIOF0_SS1 DU_DG5 GP5_14 GP5_14 203 Y31 MSIOF0_SCK DU_DB6 GP5_12 GP5_12 PWM 123 AJ5 A6 SCIFA1_RTS _ B TPU0TO2 GP0_22 GP0_22 194 AL6 A4 MSIOF1_TXD_ B TPU0TO0 GP0_20 GP0_20 196 AH5 A5 SCIFA1_TXD_ B TPU0TO1 GP0_21 GP0_21 Debug UART 208 AK11 PWM1 SCIFA2_TXD_ C GP5_30 GP5_30 2...

Page 69: ...P0_13 70 Y3 VI0_DATA3 VI 0_B3 ATADIR0 AVB_RXD5 GP2_4 GP2_4 71 Y1 VI0_CLK ATACS00 AVB_RXD1 GP2_0 GP2_0 73 Y4 VI0_DATA2 VI 0_B2 ATAWR0 AVB_RXD4 GP2_3 GP2_3 74 AJ7 D14 SCIFB1_RXD _C AVB_TXD6 RX1_B VI0_CLKENB VI0_CLKENB _B VI2_DATA6 VI2_B6 GP0_14 GP0_14 75 W6 VI0_DATA5 VI 0_B5 EX_WAIT1 AVB_RXD7 GP2_6 GP2_6 76 AK7 D15 SCIFB1_TXD _C AVB_TXD7 TX1_B VI0_FIELD VI0_FIELD_ B VI2_DATA7 VI2_B7 GP0_15 GP0_15 79...

Page 70: ...G6_B VI2_FIELD VI2_FIELD_ B GP1_9 GP1_9 7 AF4 A23 IO2 VI1_G7 VI1_G7_B VI2_G7 GP1_7 GP1_7 9 AF3 A22 MISO IO1 VI1_R5 VI1_R5_B VI2_G6 GP1_6 GP1_6 11 AF2 A21 MOSI IO0 VI1_R4 VI1_R4_B VI2_G5 GP1_5 GP1_5 13 AF1 A20 SPCLK VI1_R3 VI1_R3_B VI2_G4 GP1_4 GP1_4 15 AD1 CS0 VI1_R6 VI1_R6_B VI2_G3 MSIOF0_SS 2_B GP1_10 GP1_10 17 AL3 A13 SCIFB2_RTS _B EX_WAIT2 MSIOF2_RXD VI1_R2 VI1_R2_B VI2_G2 VI2_DATA5_ B VI2_B5_...

Page 71: ...P0_3 GP0_3 55 AH9 D2 MSIOF3_RX D_B VI3_DATA2 VI0_G6 VI0_G6_B GP0_2 GP0_2 57 AG9 D1 MSIOF3_SY NC_B VI3_DATA1 VI0_G5 VI0_G5_B GP0_1 GP0_1 GPIOs when VIN0 VIN1 in 8bit mode Or Video signals when VIN0 VIN1 in 16bit mode 18 AD2 RD WR VI1_G3 VI1_G3_B VI2_R5 SCIFA0_RXD _B GP1_20 GP1_20 20 AC1 EX_CS0 HRX1_B VI1_G5 VI1_G5_B VI2_R0 HTX0_B MSIOF0_SS 1_B GP1_12 GP1_12 37 AD3 RD CAN0_TX SCIFA0_SCK_ B GP1_19 GP...

Page 72: ...F3_SS2 DU_DG2 IIC1_SDA_C I2C1_SDA_C GP4_27 GP4_27 63 Y26 SCIFA1_RTS RTS1 MSIOF3_TXD DU_DOTCLK OUT1 HRTS0 _C GP5_3 GP5_3 65 Y25 SCIFA1_CTS CTS1 MSIOF3_RXD DU_DOTCLK OUT0 GP5_2 GP5_2 67 W25 SCIFA0_CTS HCTS1 CTS0 MSIOF3_SYNC DU_DG3 PWM0_B IIC1_SCL_C I2C1_SCL_C GP4_30 GP4_30 69 AB28 SCIFA2_SCK SCK2 MSIOF3_SCK DU_DG7 SCIF_CLK_B GP5_4 GP5_4 SCIFB1 20 U30 SSI_WS5 SCIFB1_RXD DU_EXVSYNC DU_VSYNC GP4_15 GP4...

Page 73: ...GP5_29 GP5_29 GPIOs 25 AH3 A15 SCIFB2_SCK_B ATARD1 MSIOF2_SS2 GP0_31 GP0_31 27 AG3 A18 ATAG1 GP1_2 GP1_2 28 AG4 A19 ATACS01 EX_WAIT0_B GP1_3 GP1_3 31 AH6 A2 PWM5 MSIOF1_SS 1_B GP0_18 GP0_18 32 AG1 A16 ATAWR1 GP1_0 GP1_0 35 AJ6 A3 PWM6 MSIOF1_SS 2_B GP0_19 GP0_19 43 AL2 A14 SCIFB2_TXD_ B ATACS11 MSIOF2_SS1 GP0_30 GP0_30 60 W26 MSIOF0_SS2 AUDIO_CLKO UT DU_DISP HTX0_C SCIFA2_TXD _B GP5_16 GP5_16 Rese...

Page 74: ...ardware User Guide iWave Systems Technologies Pvt Ltd 2 11 RZ G1H CPU Reference Schematic RZ G1H CPU and DDR3 reference schematic is provided below Important Note This schematic is provided only for reference without any warranty and support ...

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Page 79: ...uirement of RZ G1H Qseven SOM Table 15 Power Input Requirement Sl No Power Rail Min V Typical V Max V Max Input Ripple 1 VCC 4 75V 5V 5 25V 50mV 2 VCC_5V_SB NC NC NC NC 3 VCC_RTC3 2 8V 3V 3 3V 20 mV RZ G1H Qseven SOM is designed to work with VCC input power rail from Qseven Edge connector Optionally we can use On SOM Power IN connector to feed VCC which can be used only for standalone power up RZ ...

Page 80: ...om Qseven Edge must be active at the same time or after VCC comes up Power down Sequence PWGIN signal from Qseven Edge must be inactive at the same time or before VCC goes down VCC must go down at the same time or before VCC_RTC goes down Figure 9 Qseven SOM Power Sequence Table 16 Power Sequence Timing Item Description Value T1 VCC_RTC rise time to VCC rise time 0 ms T2 VCC rise time to PWGIN ris...

Page 81: ...MB file between USB USB3 0 and USB2 0 and SD with 1000 count VCC 1 002A 5 01W Typical Maximum Power Audio playback on SSI2 SSI3 1080p video playback on LVDS0 1080p video playback on HDMI EtherAVB 1000Mbps ping Three 8bit Camera capture USB2 0 Host to Standard SD files transfer Run the Graphics OpenGL application gles2test1 on LCD Dhrystone benchmark application VCC 1 407A 7 035W Low Power Mode Pow...

Page 82: ...mal solution Heat Sink Spreader refer the following section 4 To meet this humidity specification conformal coating needs to be done on the board By default iWave boards doesn t come with conformal coating Please contact iWave to support conformal coating 3 2 2 Heat Sink Spreader For any highly integrated System On Modules thermal design is very important factor As IC s size is decreasing and perf...

Page 83: ...REL1 1 Page 83 of 92 RZ G1H Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd Figure 10 Heat Sink Dimensions ...

Page 84: ... RoHS Compliance iWave s RZ G1H Qseven SOM is designed by using RoHS compliant components and manufactured on lead free production process 3 2 4 Electrostatic Discharge iWave s RZ G1H Qseven SOM is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board It is packed with necessary protection while shipping Do not open or use...

Page 85: ...cification Revision 2 0 The size of the PCB is 70mm x 70mm x 1 2mm as per Qseven Specification Qseven SOM mechanical dimension is shown below Please refer the Qseven Specification Revision 2 0 for more details Figure 12 Mechanical dimension of Qseven SOM Top View Note The Qseven PCB cooling plate shown above is to be used as a cooling interface between the Qseven module and the application specifi...

Page 86: ... G1H Qseven SOM PCB thickness is 1 2mm 0 15mm top side maximum height component is SPI programming Header 4 7mm followed by Inductor 3 12mm and bottom side maximum height component is expansion connector 4 30mm 0 15mm Please refer the below figure which gives height details of the RZ G1H Qseven SOM Figure 14 Mechanical dimension of RZ G1H Qseven SOM Side View ...

Page 87: ...nector at an angle of 30 as shown below in the first photo Check the Notch position of Qseven module is proper while inserting Once the Qseven module is inserted to the MXM connector properly press the board vertically down as shown below in the second photo such that the board is fixed firmly into the expansion connectors Figure 15 Qseven Module Insertion procedure Note Photo shown above is for o...

Page 88: ...21M Q74H 3D002G E008G BIC With RZ G1H Industrial grade CPU 2GB RAM 8GB eMMC with expansion and without HDMI Boot code USB3 0 SATA Industrial iW G21M Q74H 3D002G E008G LIB With RZ G1H Industrial grade CPU 2GB RAM 8GB eMMC without expansion and HDMI Linux USB3 0 PCIe Industrial iW G21M Q74H 3D002G E008G BIB With RZ G1H Industrial grade CPU 2GB RAM 8GB eMMC without expansion and HDMI Boot code USB3 0...

Page 89: ...itches Switch Switch Position ON High OFF Low SW1 QSPI Chip select is connected to On SOM SPI Flash for booting Default QSPI Chip select is connected to SPI Flash Programming Header J4 SW2 VIN0 pins are supported on Expansion Connector1 and EtherAVB Gigabit Ethernet is not supported EtherAVB Gigabit Ethernet is supported and VIN0 pins are not supported on Expansion Connector1 SW3 eMMC 4bit mode on...

Page 90: ...RZ G1H SOM through SPI Flash Programming Header J4 for programming the boot code in to the SPI flash for the first time or if boot code is corrupted This RZ G1H SPI Programmer Board has single bit DIP switch to select the SPI Flash chip select The RZ G1H SPI Programmer Board and connection to RZ G1H SOM is shown below Figure 17 RZ G1H SPI Programming Board Note Please refer the RZ G1H SOM Software...

Page 91: ... Nano ITX form factor with 120mm x 120mm size the carrier board is highly packed with all necessary interfaces on board connectors to validate complete Qseven supported features iWave Systems also supports Camera Add On module for RZ G1H Development Platform to validate RZ G1H Qseven SOM Expansion connector features For more details on RZ G1H Qseven SOM Development Platform visit the below web lin...

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