IEEE488.2 Common
Order
Copyright © Itech Electronic Co., Ltd.
36
Bit determination of standard event enable register:
Bit
position
Bit Name
Bit
Weight
7
PON
（
Power-on
）
128
6
not used
-
5
CME
（
Command error
）
32
4
EXE
（
Execution error
）
16
3
DDE
（
Device-dependent error
）
8
2
QYE
（
Query error
）
4
1
not used
-
0
OPC
（
Operation complete
）
1
*ESE?
This order can read the value of standard event status register.
Quest syntax
*ESE?
Parameter
None
Return parameter
<NR1>
*ESR?
This order can read the value of standard event status register. After executing
this order, standard event status register is reset. Bit definition of standard
event status register is as the same as the standard event status enable
register.
Quest syntax
*ESR?
Parameter
None
Return parameter
<NR1>
Reference order
*CLS
*ESE
*ESE?
