iSystem ARM HSSTP, User Manual

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5
Operation
Device overview
Device description
The front side features:

A – 40-pin HSSTP connector with 20cm high-speed cable and the following pinout:
Signal
Direction
Signal
Description
Signal Pin Pin Signal Signal description
Signal
Direction
OUT HSSTP Lane 4 Tx4_P 1 2 VREF Reference Voltage IN
OUT HSSTP Lane 4 Tx4_N 3 4 TCK/SWCLK JTAG / SWD OUT
GND 5 6 GND Ground
OUT HSSTP Lane 2 Tx2_P 7 8 TMS/SWDIO JTAG / SWD IN/OUT
OUT HSSTP Lane 2
Tx2_N
9 10 nTRST JTAG OUT
GND 11 12 GND Ground
OUT HSSTP Lane 0 Tx0_P 13 14 TDI JTAG OUT
OUT HSSTP Lane 0
Tx0_N
15 16 TDO JTAG IN
GND 17 18 GND Ground
OUT HSSTP Clock CLK_P 19 20 nSRST RESET OUT
OUT HSSTP Clock CLK_N 21 22 DBGREQ Debug Request OUT
GND 23 24 GND Ground
OUT HSSTP Lane 1 Tx1_P 25 26 DBGACK
Debug
Acknowledge
IN
OUT HSSTP Lane 1 Tx1_N 27 28 RTCK Return TCK IN
GND 29 30 GND Ground
OUT HSSTP Lane 3 Tx3_P 31 32 TRIGIN CTI Trigger Input IN
OUT HSSTP Lane 3
Tx3_N
33 34 TRIGOUT CTI Trigger Output OUT
Ground GND 35 36 GND Ground
OUT HSSTP Lane 5 Tx5_P 37 38 GND Ground
OUT HSSTP Lane 5
Tx5_N
39 40 GND Ground
Signal direction definition:
OUT - output from the Active Probe to the target microcontroller
IN - input to the Active Probe from the target microcontroller