3020-dda.ib.rev0.doc
Page 8 of 17
09/03/2006
Description of operation
See block diagrams commencing on page 4 of this manual.
Input:
The 155 Mb/s G.703 (STM-1) input signal is connected to the input circuit of the amplifier.
If no power is present then the signal will be directed to the output connector via a relay, RL4. When power is
applied the relay operates and switches the signal via the amplifier to the second RL4 relay contact and the output
connectors.
In this power fail mode, the connection from input to output is passive and so only one output can be connected.
Active path:
Input switching & equaliser:
The signal from the RL4 relay connects to the input transformer and automatic line equalisation circuit. The purpose
of this equaliser is to restore both the signal level and the leading and trailing edges of the digital signal so that
signal jitter is not introduced when the clock signal is derived in the subsequent stage.
Logic processing, reclocking and AIS detection:
The main logic processing, reclocking, error detection and operational interfacing are all performed by logic circuits
within a custom-programmed large-scale logic array (FPGA). The internal logic and functions of this IC are too
complex to describe in detail and the following is intended as a guide to function only.
Data loss detection:
Valid data is deemed to be present at the module input when 120 or more data pulses have been received in 512
nominal clock periods. In order for the data pulse to be counted, more than 60% of the minimum anticipated data
pulse must be present.
If less than 120 data pulses are counted over a period of 512 clock pulses then the data signal is deemed to be
invalid and the data loss flag is set.
If the area of a given pulse is less than 60% of the minimum anticipated (or acceptable) data pulse, after line
equalisation and shaping, then that pulse is not considered as a valid input to the count.
In any of these cases the
Data Loss
LED on the front panel of the module will light and the general alarm relay
output will be activated connecting the general alarm output contact to ground.
AIS detection:
The data processor will detect an incoming AIS (Alarm Indication Signal) (a series of all 1’s in the payload of a
frame) and will set the AIS flag and the general alarm relay output will be activated connecting the general alarm
output contact to ground.
The AIS alarm system may be disabled by a link on the main board, LK 3. This prevents the AIS detection from
operating the automatic changeover function when used in handshake configuration and prevents AIS from setting
the general alarm output. The AIS detection circuit will, however, still provide AIS indication, on the front panel
LED, if AIS is detected.
The AIS disable link does not affect the general alarm being activated by data or signal loss as described above.
Power on reset:
When power is applied to the unit, a
power on reset
signal is generated. This signal causes the processing circuit to
examine its current status and connections and restore operation to its state prior to power failure.
If the DDA is connected for stand-alone operation all alarms will be reset and normal operation will resume. If an
AIS signal is present on the data input or data is outside the prescribed limits outlined above then the general alarm
will be activated after the normal detection period has elapsed from the P.O.R. signal being initiated.
Data signal output drivers.
Four separate output drivers drive the outputs, one of which goes via relay RL4 to O/P 3. In the event of a power
failure the input is passively switched to O/P 3.
Note that the
Mon. Output
on the front panel of the module is obtained in the same manner as the outputs on the rear
of the module.
IRT
Communications
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