IPC Solutionki PC104-386L-2M, User Manual

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NAGASAKI Corporation
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Divisor Latch (LS, MS)
LS MS
Bit 0: Bit 0 Bit 8
Bit 1: Bit 1 Bit 9
Bit 2: Bit 2 Bit 10
Bit 3: Bit 3 Bit 11
Bit 4: Bit 4 Bit 12
Bit 5: Bit 5 Bit 13
Bit 6: Bit 6 Bit 14
Bit 7: Bit 7 Bit 15
Desired Baud Rate Divisor Used to Generate 16x
Clock
300 384
600 192
1200 96
1800 64
2400 48
3600 32
4800 24
9600 12
14400 8
19200 6
28800 4
38400 3
57600 2
115200 1
Table 2-6 Serial Port Divisor Latch
2.6 PARALLEL PORTS
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Register Address
Port Address Read/Write Register
Base + 0 Write Output data
Base + 0 Read Input data
Base + 1 Read Printer status buffer
Base + 2 Write Printer control
latch
Table 2-7 Registers’ Address
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Printer Interface Logic
The parallel portion of the SMC37C669 makes the attachment of various devices that accept
eight bits of parallel data at standard TTL level.
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Data Swapper
The system microprocessor can read the contents of the printer’s Data Latch through the Data
Swapper by reading the Data Swapper address.
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