INMP441
THEORY OF OPERATION
The INMP441 is a high-performance, low-power, digital-output, omni-directional MEMS microphone with a bottom port. The
complete INMP441 solution consists of a MEMS sensor, signal conditioning, an analog-to-digital converter, anti-aliasing filters,
power management, and an industry-standard 24-bit I²S interface.
The INMP441 complies with the TIA-920
Telecommunications Telephone Terminal Equipment Transmission Requirements for
Wideband Digital Wireline Telephones
standard.
UNDERSTANDING SENSITIVITY
The casual user of digital microphones may have difficulty understanding the sensitivity specification. Unlike an analog microphone
(whose specification is easily confirmed with an oscilloscope), the digital microphone output has no obvious unit of measure.
The INMP441 has a nominal sensitivity of
−
26 dBFS at 1 kHz with an applied sound pressure level of 94 dB. The units are in decibels
referred to full scale. The INMP441 default full-scale peak output word is 2
23
− 1
(integer representation), and
−
26 dBFS of that scale
is (2
23
− 1
) × 10
(−26/20)
= 420,426. A pure acoustic tone at 1 kHz having a 1Pa RMS amplitude results in an output digital signal whose
peak amplitude is 420,426.
Although the industry uses a standard specification of 94 dB SPL, the INMP441 test method applies a 104 dB SPL signal. The higher
sound pressure level reduces noise and improves repeatability. The INMP441 has excellent gain linearity, and the sensitivity test
result at 94 dB is derived with very high confidence from the test data.
POWER MANAGEMENT
The INMP441 has three different power states: normal operation, standby mode, and power-down mode.
Normal Operation
The microphone becomes operational 2
18
clock cycles
(85 ms with SCK at 3.072
MHz) after initial power-up. The CHIPEN pin then
controls the power modes. The part is in normal opera
tion mode when SCK is active and the
CHIPEN pin is high.
Standby Mode
The microphone enters standby mode when the serial-
data clock SCK stops and CHIPEN is high. Normal operation resumes 2
14
clock
cycles (5 ms with SCK at 3.072 MHz) after SCK restarts.
The INMP441 should not be transitioned from standby to power-down mode, or vice versa. Standby mode is only intended to be
entered from the normal operation state.
Power-Down Mode
The microphone enters power-
down mode when CHIPEN is low, regardless of the SCK operation. Normal mode operation resumes
2
17
SCK clock cycles (43 ms with
SCK at 3.072
MHz) after CHIPEN
returns high while SCK is active.
It always takes 2
17
clock cycles to restart the INMP441 after
V
DD
is applied.
It is not recommended to supply active clocks (WS and SCK) to the
INMP441 while there is no power supplied to
VDD
. Doing this
continuously turns on ESD protection diodes, which may affect long-term reliability of the microphone.
Startup
The microphones have zero output for the first 2
18
SCK clock cycles (85ms with SCK
at 3.072 MHz) following power-up.
Page 10 of 21
Document Number: DS-INMP441-00
Revision: 1.1
