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AN1260.1

January 26, 2010

Description of Jumper Settings

JP1 - A shunt installed on JP1 connects the input 
source from connector J1 to the circuit if input current 
measurement is not needed. The shunt can be 
replaced by a current meter if input current 
measurement is needed, as shown in Figure 1. 

JP2 - A shunt installed on JP2 connects the input 
source from the USB port connector to the USB pin if a 
USB port is used for the evaluation.

JP3 - Connects the EN pin to a pull-up voltage or GND. 
The pull-up voltage is regulated 3.3V from the input 
source (either Cradle or USB). If there is no shunt 
installed on JP3, the EN pin is internally pulled down to 
logic LOW, which enables the charger. If a shunt is 
installed across the two jumper pins labeled as 
“Enable”, the EN pin is driven to logic LOW, the charger 
is enabled, same as floating. If the shunt is installed 
across the two jumper pins labeled as “Disable”, the EN 
pin is driven to logic HIGH, which disables the charger.

JP4 - ON/OFF control for USB input. Install a jumper 
shunt on USB OFF position to turn off the USB charge 
but has no impact on the cradle input charge.

JP5 - Parallels an additional 11.8k resistor to the IMIN 
pin (total R

IMIN

 = 5.9k), such that the End-of-Charge 

Current will be increased to 93mA (R

IMIN

 is 11.8k and 

the EOC current is 46.5mA without the shunt). 

JP6 - A shunt installed on JP6 connects the BAT pin to 
the output connector J3 if output current measurement 
is not needed. The shunt can be replaced by a current 
meter if output current measurement is needed as 
shown in Figure 1. 

JP7 - Parallels an additional 23.7k resistor to the ICDL 
pin (total R

ICDL

 = 11.85k), such that the cradle charge 

current will be increased to 0.575A (R

IREF

 is 23.7k and 

the charge current is 0.28A if the shunts on both JP7 
and JP8 are removed).

JP8 - Parallels an additional 14.7k resistor to the ICDL 
pin (when JP7 is installed, total R

ICDL

 = 6.56k), such 

that the cradle charge current will be increased to 
1.04A.

PS1

-     +

PS3

+     -

+         -

E-LOAD

I1

PS2

-     +

I2

FIGURE 1. CONNECTION OF INSTRUMENTS

Application Note 1260

Summary of Contents for ISL9214AEVAL1Z

Page 1: ...uggesting the Space Saving Advantage of the Typical Components Assembly Both Inputs Accept Voltage up to 28V Flexible Power Connectors Each with a Hook and a Solder Pad Providing Variety to Users USB Port On Board Accepts Power Directly From USB Cable Convenient Jumpers for Programming the Charge Current Charge Mode and for Current Measurement 3 5x2 5 Square Inches Board Size Handy for Evaluation ...

Page 2: ...s 8 9 and 10 respectively Step 12 Slowly reduce the DC electronic load current until the green LED turns off The current meter I2 should read about 47mA EOC current Step 13 Insert a jumper shunt on JP5 and repeat Step 12 the current meter I2 should read 93mA EOC current For USB Input Step 1 Connect a 5V supply PS2 to USB with the current limit set at 0 7A Step 2 Connect a 3 7V supply PS3 to BAT J3...

Page 3: ... is driven to logic HIGH which disables the charger JP4 ON OFF control for USB input Install a jumper shunt on USB OFF position to turn off the USB charge but has no impact on the cradle input charge JP5 Parallels an additional 11 8k resistor to the IMIN pin total RIMIN 5 9k such that the End of Charge Current will be increased to 93mA RIMIN is 11 8k and the EOC current is 46 5mA without the shunt...

Page 4: ... installed Sets CRDL and USB EOC current to 93mA JP6 Shunt installed Connects BAT to J3 JP7 Shunt installed Sets CRDL charging current to 0 575A if shunt on JP7 is not installed JP8 Shunt installed Sets CRDL charging current to 1 04A if shunt on JP7 is also installed R5 23 7k CRDL 1 USB 2 PPR 3 CHG 4 EN 5 IMIN 6 USBON 7 GND 8 ICDL 9 BAT 10 U1 ISL9214 C3 1µF C2 4 7µF 35V C1 4 7µF 35V C5 0 1µF C6 0 ...

Page 5: ... 1 C7 10µF 6 3V Tantalum 1206 ECS T0JY106R Panasonic 13 1 C8 47µF 6 3V X5R Ceramic 1210 ECJ 4YB0J476M Panasonic 14 1 C3 1µF 25V X5R Ceramic 0805 ECJ 2FB1E105K Panasonic 15 3 C4 C5 C6 0 01µF 50V X7R Ceramic 0402 C0402C103K5RACTU Kemet 16 2 J1 J3 2 54mm Center Header 2 CKT 22 11 2022 Molex 17 3 CRDL USB VBAT Test point Red 5010 Keystone 18 6 PPR CHG EN IMIN USBON Test point Yellow 5014 Keystone ICDL...

Page 6: ...6 AN1260 1 January 26 2010 PCB Layout FIGURE 3 SILK LAYER FIGURE 4 TOP LAYER Application Note 1260 ...

Page 7: ... time without notice Accordingly the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding For information regarding Intersil Corporation and its products see www intersil com AN1260 1 January 26 2010 FIGURE 5 BOTTOM LAYER PCB Layout Continued Application Note 1260 ...

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