Application Note 1946
2
AN1946.0
July 7, 2014
Submit Document Feedback
Functional Description
The ISL78268 is a high voltage synchronous buck controller with
integrated 2A source/3A sink MOSFET drivers. The device
operates over a wide input voltage range, 5V to 55V, and
withstands up to 60V. The full synchronous operation of
ISL78268 enables high conversion efficiency in continuous
conduction mode. Also, the device provides Diode Emulation
mode (DE mode) for efficiency improvement in light load
operation. The ISL78268 also provides comprehensive
protection features of input and output overvoltage,
cycle-by-cycle peak current limiting, average output current
limiting and thermal protection.
The ISL78268EVAL1Z evaluation board is shown in
Figures 2
and
3
. The board supports quick evaluation of various features of
the ISL78268. The ISL78268EVAL1Z’s default configuration is
for 12V at VOUT, with a peak current limit (OC1: cycle-by-cycle) of
9.3A, peak current protection (OC2: hiccup/ latch-off) 12.4A, and
an average current limit of 4A.
The operation mode of DE mode or Forced PWM mode is
selectable by the connection of IMON/DE pins. The fault
response of hiccup or latch-off is selected by the connection of
HIC/LATCH pin. Voltage or waveforms of key signals such as VCC,
SS, FB, COMP, EN, CLKOUT, PH etc., are pulled out to the monitor
pins for easy measurement.
Table 1
shows more details of
connector/monitor-pin descriptions.
Figure 4
shows the schematics of this evaluation board and
Table 3
shows its BOM list. The layout information of the board
are shown in
Figures 5
through
10
.
Figures 11
through
24
show the performance data taken with
this evaluation board with default configuration.
Operating Range
The default configuration is shown in
“Specification (Default
Setting)” on page 1
.
The board setting can be changed by changing the connections
of setting pins or replacing the resistors and/or capacitors
populated on the board. Some examples are described as
follows:
• The switching frequency on the ISL78268EVAL1Z is fixed at
300kHz. To change the frequency, replace the R
18
which is
connected between FSYNC and GND. Please refer to the
“Internal Clock Frequency Setting” section in Datasheet for
detail. Also, the clock can be synchronized with the external
clock source by input square wave at FSYNC pin. The external
clock frequency range will be 50kHz to 1.1MHz.
• The output voltage of ISL78268EVAL1Z is fixed at 12V in
default setting. This can be changed by replacing feedback
resistor R
1
. When changing the feedback resistor, the
minimum input voltage on the board will be changed
accordingly. If changing the output voltage, be careful because
the minimum input voltage will be limited by the high-side
MOSFET minimum off time (t
MINOFF_UG
) of the ISL78268,
which is 285ns (typ). Also, the maximum input voltage will be
limited by the minimum on time of high-side MOSFET
(t
MINON_UG
) which is 300ns(typ).
• The operation mode of DE mode or Forced PWM mode is
selectable by the connection of IMON/DE pins.
• The fault response of hiccup or latch-off is selected by the
connection of HIC/LATCH pin.
• The average output current limit can be adjusted by replacing
the resistor connected to IMON/DE pin (R
4
). For the setting of
the average current limit, please refer to “Current Sensing” and
“Average Constant Current Control” sections in the
ISL78268
datasheet.
• The cycle-by-cycle peak current limit can be changed by
replacing the current sense resistor (R
10
) and/or gain set
resistor (R
8
+R
9
). Please refer to “Current Sensing” and “Cycle-
by-Cycle Peak Overcurrent Limiting/Protection” sections in
ISL78268
datasheet for the detailed relation between R
10
and/or R
8
+R
9
and peak current limit.
PCB Layout Guideline
The ISL78268EVAL1Z layout is optimized for electrical and
thermal performances. Key considerations are:
• Most of switching nodes are patterned on the top layer with
simple and short routing.
• 4x4 pattern of 300µm vias under the ISL78268 thermal pad
are connected to large copper GND planes (layers 2, 3 and 4)
for effective thermal performances.
• Maximize the copper layers of the Power Transistor Drain node
by connecting each layers with multiple via for the effective
thermal performances.
• Place the input ceramic capacitor as close as possible to the
VIN pin.
• Place the ceramic capacitor as close as possible to minimize
the ringing associated by the parasitic inductance and
capacitance in the high current transition loop.
• Keep the traces of current sense lines symmetric as much as
possible to avoid the offset and noise injection.
• The board size is 2.65 in. x 2.85 in. with 4-layers and 2oz
copper.
