User Guide 046
6
U
G
04
6.0
Au
gust 2
8
, 20
1
5
Submi
t D
ocument
Feedba
ck
ISL70003ASEHEV2Z Circuit Schematic
FIGURE 10. ISL70003ASEHEV2Z SCHEMATIC
RELEASED BY:
DRAWN BY:
SHEET
HRDWR ID
DATE:
DATE:
DATE:
TESTER
FILENAME:
MASK#
REV.
OF
DATE:
ENGINEER:
TITLE:
UPDATED BY:
TIM KLEMANN
06/22/2015
EVALUATION / DEMO
BOARD SCHEMATIC
ISL70003ASEHEV2Z
ISL70003ASEH
1
1
LARRY GOUGH
PLACE CC1 - CC8 CLOSE TO U1
*
GND
GND
GND
PLACE CC6 CLOSE TO J2 AND GND
TO OUTPUT CAPACITOR GROUND.
PIN 7 TO USE AN ISOLATED TRACE
NOTE: *
COMP
IMON
LX
OCA
OCB
POR
PVIN
PVIN
REF
REF_OUT
VO
U
T
VOUT
VOUT
VOUT
VREFA
VREFD
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
CI
N2
150UF
20K
RE
NA
B
LE
C1
2700P
F
150UF
CO
1
1000P
F
C3
10UF
CC1
R3
357
10UF
CO
3
390P
F
CT
CC2
10UF
22K
RT
1
R2
51.
1K
TPB2
C2
12P
F
0.
1UF
CC8
25K
R1
100K
PORR1
CC4
0.
1UF
TP2
0.
010UF
CP
O
R
TP1
5.49K
R4
TP4
7.
15K
P
O
RR2
TP3
R5
49.
9
0.47UF
C4
TP5
CS
S
0.
1UF
C5
0.47UF
0.22UF
CREF
C6
0.47UF
D2
RD2
1K
2N7002-7-F
Q2
1
2
3
C7
6800P
F
CP
G
0.
01UF
4.
02K
RO
CB
RP
UL
L1
3K
RO
CA
4.
02K
REF
BU
FO
U
T
BU
FI
N
-
VREFA
AVDD
AGND
DGND
VREF_OUTS
DVDD
VREFD
NI
P
G
ND1
P
G
ND2
LX
2
PVIN
2
SG
N
D
IM
O
N
NC/
HS
PVIN3
LX3
PVIN4
LX5
DE
PVIN8
PGND7
PGND8
SEL
2
SEL
1
PVIN
9
LX
9
P
G
ND9
PVIN
10
LX8
PVIN6
LX6
PGND6
PGND5
PVIN5
LX4
PVIN
1
PGND3
PGND4
OS
C
E
TA
LX
1
OS
C
E
TB
BU
FI
N
+
SS_CAP
HS PAD
P
GOOD
LX
10
P
G
ND10
ENABLE
SYNC
GN
D
GN
D
GN
D
GN
D
RT/CT
FSEL
GND
LX7
PVIN7
FB
VERR
POR_VIN
U1
ISL70003ASEHVFE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
C8
6800P
F
10K
RI
M
O
N
DNP
C9
C10
1000P
F
1
R10
TPB1
CI
N1
150UF
3.3UH
L1
