Intersil ISL68200 Series, User Manual

Page: 4 / 22

UG067 Rev.2.00 Page 4 of 22
Aug 23, 2017
ISL68200DEMO1Z
Design Modifications
Any modifications to the design will require new L/DCR matching
for a different inductor, a divider on the PROG pins for a different
operational configuration, RSEN1 for OCP, and an IOUT network
for accurate digital IOUT, a higher input capacitor rating to
support higher than 16V input, and a higher output capacitor
rating to support higher than 4V output. Refer to the
ISL68200
datasheet and PowerNavigator software for proper design
modifications including L/DCR matching, thermal
compensation, OCP, and digital I
OUT
fine-tuning.
Two examples are provided in Table 1 , showing the
recommended design modifications to accommodate the
application cases with 5V and 3.3V output voltages. Some
fine-tuning might be needed depending upon the rework and
final layout design.
For the 5V input voltage applications with 4.5V < V
IN
< 5.5V
requirement, the VIN, VCC, PVCC, and 7VLDO pins should be
shorted together, to connect with the input supply for optimal
performance; R
12
should be removed as well.
Note that all devices in the same bus should set different
addresses for unique identification and proper communication.
JP2, JP3, JP9, and JP10 connectors are designed to cascade
many Intesil’s solutions for easy communication and system
evaluation before the system integration and design.
TABLE 1. DESIGN EXAMPLES
REFERENCE
DESIGNATOR 5.0V AT 16A 3.3V AT 16A 3.3V AT 30A COMMENTS
L1 680nH, 1.72m Ω
Vendor: Wurth Electronic;
Part Number: 744334006
470nH, 0.165m Ω
Vendor: Wurth Electronic;
Part Number: 744309047
Reduce Output ripple current; typically higher
voltage output needs higher inductance.
CO5, CO6, CO8,
CO9
100µF/X5R/6.3V/1206
Vendor: Murata;
Part Number: GRM21BR60J107ME11
Increase C
OUT
rating to support higher V
OUT.
Also capacitance of ceramic capacitors
decreases with increased output voltage.
PROG1 (DC) DFh BFh BFh Set correct V
BOOT
= V
OUT
R
3
147k, 1% 105k, 1% 105k, 1%
PROG2 (DD) A0h BFh BFh Set Different PMBus Addresses as needed
T
COMP
= 15
PFM DISABLED
R
5
105k, 1% DNP DNP
R
6
DNP 105k, 1% 105k, 1%
PROG3 (DE) 0Dh 0Dh 0Dh Set AV = 13
f
SW
= 500kHz
OCP = Retry
25kHz Clamp Disabled
R
8
24.3k, 1% 24.3k, 1% 24.3k, 1%
R
9
16.9k, 1% 16.9k, 1% 16.9k, 1%
PROG4 (DF) 08h 08h 08h Set RR = 400k
SS = 1.25mV/µs
AVMLTI = 1 x
R
10
15k, 1% 15k, 1% 15k, 1%
R
11
29.4k, 1% 29.4k, 1% 29.4k, 1%
R
P1
4.99k, 1% 4.99k, 1% 3.57k, 1% L/DCR Matching
R
SEN1
536, 1% 536, 1% 62, 1% Set OCP
R
13
11k, 1% 11k, 1% 15k, 1% Set I
OUT
to 1A/1A Slope
R
14
TBD TBD TBD Pull-up value depends upon final layout
design
NOTE:
1. Some fine-tuning might be needed depending upon the rework and final layout design.