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UG067 Rev.2.00

Page 2 of 22

Aug 23, 2017

ISL68200DEMO1Z

Demonstration Board 

Description

The ISL68200DEMO1Z provides all circuitry required to 
demonstrate the key features of the ISL68200. A majority of the 
features of the ISL68200, such as optimal transient response 
with Intersil’s R4 Modulator, 8-bit programmable boot voltage 
levels, selectable switching frequency in continuous conduction 
mode, selectable PFM operation option for improved light-load 
efficiency, power-good monitor for soft-start and fault detection, 
over-temperature protection, output overcurrent and short-circuit 
protection, and output overvoltage protection are available on 
this demonstration board. 

Figure 1

 shows a simplified schematic diagram of the 

ISL68200DEMO1Z board. 

Figure 6

 shows the detailed 20A buck 

solution schematics, while 

Figure 7

 shows the I/O connectors, 

auxiliary circuits and on-board transient circuits. 

Figures 8

 

through 

30

 show typical performance data and 

Figures 31

 

through 

36

 show the PCB board layout. The default programming 

pins setting is given on the upper right corner of 

Figure 7

, and the 

Bill of Materials (BOM) is included for reference beginning on 

page 9

.

The ISL68200DEMO1Z board can run by itself without a serial 
bus communication. The operational configuration is fully 
programmable using programming pins (PROG1-4). 

The ISL68200 however, uses the PMBus/SMBus/I

2

C protocol 

and provides the flexibility for digital power management and 
performance optimization before finalizing the hardware 
configuration on the programming pins. 

The buck regulator in the ISL68200DEMO1Z board is a single 
input rail design, that is, everything is biased by the input supply 
(typically 12V). The resistor divider on the EN pin (R

4

 and R

12

can set the input supply undervoltage protection level and its 
hysteresis. The “ENABLE” switch is a hardware operational 
control, alternately, the serial bus ON_OFF_CONFIG and 
OPERATION commands can be used for software operational 
control. 

Furthermore, an on-board transient load, as shown in 

Figure 7

with both di/dt and load step amplitude is controlled by a 
function generator. Because this auxiliary circuit draws more 
than 10A of bias current, the jumper on JP5 should be removed 
for accurate efficiency measurement. 

Intersil’s PowerNavigator

 

evaluation software is compatible with 

Windows operating systems and can be used to evaluate the 
serial bus functionality of the ISL68200. The software and user 
guide can be found at: 

http://www.intersil.com/powernavigator

Quick Start Guide

Stand-Alone Operation

1. Set the ENABLE switch to the “OFF” position.
2. Connect a power supply (off) to input connectors (J4-VIN and 

J3-GND). 

3. Set the input power supply voltage level (no more than 15V) 

and current limiting (no more than 1A for 0A load).

4. Turn the power supply on.
5. Set the ENABLE switch to the “ON” position.
6. Increase the power supply current limit enough to support 

more than the full load. 

7. Apply load to the output connectors (J1-VOUT and J2-SGND). 
8. Monitor operation using an oscilloscope.

PMBus Operation

1. Connect the supplied dongle to J8.
2. Connect the supplied USB cable from the computer to the 

dongle.

3. After the input power supply turns on, open the 

PowerNavigator™ evaluation software.

4. Select the detected ISL68200 device (Address - 60h) and 

follow Intersil’s PowerNavigator operation guide.

5. Monitor and configure the board using PMBus commands in 

the evaluation software.

FIGURE 2. DEMONSTRATION BOARD TOP VIEW

FIGURE 3. DEMONSTRATION BOARD BOTTOM VIEW

Summary of Contents for ISL68200 Series

Page 1: ...om Intersil s website and be used to evaluate the full PMBus functionality of the part using a PC running Microsoft Windows Related Literature For a full list of related documents visit our website IS...

Page 2: ...biased by the input supply typically 12V The resistor divider on the EN pin R4 and R12 can set the input supply undervoltage protection level and its hysteresis The ENABLE switch is a hardware operati...

Page 3: ...power up down sequencing and operational configuration without a soldering iron Load Transient The on board transient load can be controlled by a function generator whose inputs are connected to FG_D...

Page 4: ...tion JP2 JP3 JP9 and JP10 connectors are designed to cascade many Intesil s solutions for easy communication and system evaluation before the system integration and design TABLE 1 DESIGN EXAMPLES REFE...

Page 5: ...ce X7R 1 F in close proximity to the VCC pin and the system ground plane SCL SDA Yes 50kHz to 1 25MHz signal when the SMBus PMBus or I2C is sending commands Pairing up with SALERT and routing carefull...

Page 6: ...4 7 F in proximity to the PVCC pin and the system ground plane TABLE 2 DESIGN AND LAYOUT CHECKLIST Continued PIN NAME NOISE SENSITIVITY DESCRIPTION TABLE 3 TOP LAYOUT TIPS NUMBER DESCRIPTION 1 The lay...

Page 7: ...TP Retry 400kHz AV 42 PROG4 00h SS 1 25mV us RR 200k Ohm AVMULTI 1X 50 5 0 X 5 9 0402 size NCP15XH103J03RC 9 2 5 1 96 1 6571 6 1 227 39 39 39 39 39 39 39 6 57 6 6 9 3 22 3 6 9287 1 9287 17 287 39 9 8...

Page 8: ...DONGLE FROM PREQUEL TO SEQUEL ON LEFT OF BOARD MALE ON RIGHT OF BOARD FEMALE 2 5 72 2 5 17 5 This board only uses SDA SCL SALRT GND signals Pull Up Impedance to Be Ajusted for How Many Boards are con...

Page 9: ...3EKF1502V 1 R9 29 4k 1 SM0603 YAGEO RC0603FR 0729K4L 4 R10 R15 R16 R17 10k 1 SM0603 VENKEL CR0603 10W 1002FT 1 R12 24 9k 1 SM0603 PANASONIC ERJ 3EKF2492V 1 R13 9 53k 1 SM0603 YAGEO 9C06031A9531FKHFT 2...

Page 10: ...X 131 4353 00 4 TP3 TP4 TP5 TP6 Test Point MTP500x KEYSTONE 5002 2 VCC12 FG_DRIVE Test Point RED MTP500x KEYSTONE 5000 2 VIN_GND FG_GND Test Point BLACK MTP500x KEYSTONE 5001 4 R32 R33 R36 R37 3 1 SM0...

Page 11: ...A SLOPE 1 EFFICIENCY ERROR DIGITAL I OUT LOAD A 80 81 82 83 84 85 86 87 88 89 90 91 92 0 2 4 6 8 10 12 14 16 18 20 22 24 LOAD CURRENT A VOUT 0 8V VOUT 1V VOUT 1 2V VOUT 1 5V VOUT 1 8V EFFICIENCY 83 8...

Page 12: ...3 94 95 0 2 4 6 8 10 12 14 16 18 20 22 24 LOAD CURRENT A VOUT 0 8V VOUT 1V VOUT 1 2V VOUT 1 5V VOUT 1 8V EFFICIENCY 5 0 5 10 15 20 25 30 75 77 5 80 82 5 85 87 5 90 0 2 4 6 8 10 12 14 16 18 20 22 24 LO...

Page 13: ...IN PFM MODE CH1 VOUT CH2 PHASE FIGURE 23 STEP RESPONSE AT PWM MODE VOUT 1V fSW 400kHz LOAD PROFILE 0 25A TO 12 75A AT 25A s CH1 VOUT CH2 LOAD FIGURE 24 STEP RESPONSE AT PFM ENABLED MODE VOUT 1V fSW 40...

Page 14: ...PHASE FIGURE 28 OVERVOLTAGE PROTECTION CH1 VOUT CH2 PGOOD CH3 LGATE FIGURE 29 OVER TEMPERATURE PROTECTION AT 1A LOAD CH1 VOUT CH2 LOAD CH3 PHASE CH4 NTC FIGURE 30 POWER DOWN AT VOUT 1V 1A LOAD CH1 VO...

Page 15: ...UG067 Rev 2 00 Page 15 of 22 Aug 23 2017 ISL68200DEMO1Z ISL68200DEMO1Z Board Layout FIGURE 31 PCB TOP ASSEMBLY...

Page 16: ...UG067 Rev 2 00 Page 16 of 22 Aug 23 2017 ISL68200DEMO1Z FIGURE 32 PCB TOP LAYER ISL68200DEMO1Z Board Layout Continued...

Page 17: ...UG067 Rev 2 00 Page 17 of 22 Aug 23 2017 ISL68200DEMO1Z FIGURE 33 PCB INNER LAYER 2 TOP VIEW ISL68200DEMO1Z Board Layout Continued...

Page 18: ...UG067 Rev 2 00 Page 18 of 22 Aug 23 2017 ISL68200DEMO1Z FIGURE 34 PCB INNER LAYER 3 TOP VIEW ISL68200DEMO1Z Board Layout Continued...

Page 19: ...UG067 Rev 2 00 Page 19 of 22 Aug 23 2017 ISL68200DEMO1Z FIGURE 35 PCB INNER LAYER 4 TOP VIEW ISL68200DEMO1Z Board Layout Continued...

Page 20: ...UG067 Rev 2 00 Page 20 of 22 Aug 23 2017 ISL68200DEMO1Z FIGURE 36 PCB INNER LAYER 5 TOP VIEW ISL68200DEMO1Z Board Layout Continued...

Page 21: ...UG067 Rev 2 00 Page 21 of 22 Aug 23 2017 ISL68200DEMO1Z FIGURE 37 PCB BOTTOM LAYER TOP VIEW ISL68200DEMO1Z Board Layout Continued...

Page 22: ...is current before proceeding For information regarding Intersil Corporation and its products see www intersil com ISL68200DEMO1Z UG067 Rev 2 00 Page 22 of 22 Aug 23 2017 Copyright Intersil Americas L...

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