Intergraph RealiZm Graphics V25, Hardware User'S Manual

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The following figure shows the back of a Z25 or V25 graphics board:
PCIDMA
The PCIDMA application-specific integrated circuit (ASIC) is a multichannel, direct memory
access (DMA) engine capable of burst transfers. For OpenGL requests, the Rasterization
Accelerator uses a DMA to send vertex data through the PCIDMA to the graphics engine first-
in-first-out (FIFO).
Graphics Engine and Texture Processor
The Graphics Engine ASIC and the Texture Processor are physically separate entities for the
Z10, and integrated within the same ASIC for the Z13, Z25, and the V25.
The Graphics Engine is the main graphics processor for the graphics board and the core of the
Rasterization Accelerator. It takes vertex data from the graphics FIFO and produces spans of
pixel data. The Graphics Engine sends the data to the Frame Buffer over a high-speed pixel
path called the Image/Z (IZ) bus. If texture memory is present, texturing of the pixels occurs
before transfers of data on the IZ bus.
The Graphics Engine uses four major logic blocks to perform the pixel rasterization. They
are: (1) request handler, (2) slope calculation, (3) span generation, and (4) pixel interpolation.
Video Memory