Dual-Core Intel® Xeon® Processor LV and Intel
®
3100 Chipset
January 2007
User’s Manual
Order Number: 315879-002
13
Product Description
1.3.2
DDR2 DIMM Ordering Overview
Figure 2
shows the DIMM ordering and location.
Note:
Figure 2, “Four-DIMM Implementation” on page 13
* signifies that the chipselect is also
routed to these DIMMS.
The platform requires DDR2-400 DIMMs to be populated in order, starting with the
DIMM furthest from Intel
®
3100 Chipset in a “fill-farthest” approach (see
Figure 2 on
page 13
). In addition, dual-rank DIMMs must be populated farthest from Intel
®
3100
Chipset when a combination of single-rank and dual-rank DIMMs are used. This
recommendation is based on the chip select and on-die termination signals routing
requirements of the DDR2-400 interface. Intel recommends that you check for correct
DIMM placement during BIOS initialization and that all designs follow the DIMM
ordering, clock enable routing, command clock routing, and chip select routing shown
in
Figure 2 on page 13
. This addressing must be maintained to be compliant with the
BIOS code.
The two DIMMs that are provided with the development kit are 1Gb single-rank DIMMs.
If other memory is used follow the illustrations in
Figure 3
,
Figure 4
, and
Figure 5
.
Figure 3
shows how to populate four single-rank DIMMs.
Figure 4
shows how to
populate one dual-rank and two single-rank DIMMs.
Figure 5
shows how to populate
two dual-rank DIMMs.
Figure 2.
Four-DIMM Implementation
Intel® 3100
Chipset
D
I
M
M
3
D
I
M
M
2
D
I
M
M
1
D
I
M
M
0
Fill Fourth Fill Third
Fill Second
Fill First
Dual-Rank DIMMs
Single-Rank DIMMs utilize all 4 DIMMs
