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Intel® Xeon® Processor 3500 Series Datasheet Volume 1

9

Introduction

1

Introduction

The Intel

®

Xeon

®

Processor 3500 Series are intended for Uni-processor (UP) and

workstation systems. Several architectural and microarchitectural enhancements have
been added to this processor including four processor cores in the processor package
and increased shared cache.

The Intel Xeon Processor 3500 Series is the first multi-core processor to implement key
new technologies:

• Integrated memory controller
• Point-to-point link interface based on Intel

®

QuickPath Interconnect (Intel

®

QPI)

shows the interfaces used with these new technologies.

Note:

In this document the Intel Xeon Processor 3500 Series will be referred to as “the

processor.”

The processor is optimized for performance with the power efficiencies of a low-power
microarchitecture.

This document provides DC electrical specifications, differential signaling specifications,
pinout and signal definitions, package mechanical specifications and thermal
requirements, and additional features pertinent to the implementation and operation of
the processor. For information on register descriptions, refer to the

Intel® Xeon®

Processor 3500 Series Datasheet, Volume 2

.

The processor is a multi-core processor built on the 45 nm process technology, that
uses up to 130 W thermal design power (TDP). The processor features an Intel QPI
point-to-point link capable of up to 6.4 GT/s, 8 MB Level 3 cache, and an integrated
memory controller.

The processor supports all the existing Streaming SIMD Extensions 2 (SSE2),
Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The
processor supports several Advanced Technologies: Intel

®

64 Technology (Intel

®

64),

Enhanced Intel SpeedStep

®

Technology, Intel

®

Virtualization Technology (Intel

®

VT),

Intel

®

Turbo Boost Technology, and Intel

®

Hyper-Threading Technology.

Figure 1-1. High-Level View of Processor Interfaces

Processor

Intel

®

QuickPath

Interconnect (Intel

®

QPI)

CH 0

CH 1

CH 2

System

Memory

(DDR3)

«
...
7
8
9
10
11
...
»

Summary of Contents for Xeon 3500 Series

Page 1: ...Document Number 321332 002 Intel Xeon Processor 3500 Series Datasheet Volume 1 July 2009 ...

Page 2: ...etails on which processors support HT Technology see http www intel com products ht hyperthreading_more htm Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality 64 bit computing on Intel architecture requires a ...

Page 3: ...oltage Validation 30 3 Package Mechanical Specifications 31 3 1 Package Mechanical Drawing 31 3 2 Processor Component Keep Out Zones 34 3 3 Package Loading Specifications 34 3 4 Package Handling Guidelines 34 3 5 Package Insertion Specifications 34 3 6 Processor Mass Specification 35 3 7 Processor Materials 35 3 8 Processor Markings 35 3 9 Processor Land Coordinates 36 4 Intel Xeon Processor 3500 ...

Page 4: ...s 21 2 3 VCC Static and Transient Tolerance Load Lines 25 2 4 VTT Static and Transient Tolerance Load Line 27 2 5 VCC Overshoot Example Waveform 30 3 1 Processor Package Assembly Sketch 31 3 2 Processor Package Drawing Sheet 1 of 2 32 3 3 Processor Package Drawing Sheet 2 of 2 33 3 4 Processor Top Side Markings 35 3 5 Processor Land Coordinates and Quadrants Bottom View 36 6 1 Processor Thermal Pr...

Page 5: ...28 2 14 PWRGOOD Signal Group DC Specifications 28 2 15 Control Sideband Signal Group DC Specifications 29 2 16 VCC Overshoot Specifications 29 3 1 Processor Loading Specifications 34 3 2 Package Handling Guidelines 34 3 3 Processor Materials 35 4 1 Land Listing by Land Name 38 4 2 Land Listing by Land Number 56 5 1 Signal Definitions 75 6 1 Processor Thermal Specifications 80 6 2 Processor Thermal...

Page 6: ...video audio encryption and 3D performance New accelerators for improved string and text processing operations Power Management capabilities System Management mode Multiple low power states 8 way cache associativity provides improved cache hit rate on load store operations System Memory Interface Memory controller integrated in processor package 3 channels 2 DIMMs channel supported 6 total 24 GB ma...

Page 7: ...Intel Xeon Processor 3500 Series Datasheet Volume 1 7 Revision History Revision Number Description Date 321332 001 Public release March 2009 Added Processor Information for W3580 W3550 July 2009 ...

Page 8: ...8 Intel Xeon Processor 3500 Series Datasheet Volume 1 ...

Page 9: ...differential signaling specifications pinout and signal definitions package mechanical specifications and thermal requirements and additional features pertinent to the implementation and operation of the processor For information on register descriptions refer to the Intel Xeon Processor 3500 Series Datasheet Volume 2 The processor is a multi core processor built on the 45 nm process technology th...

Page 10: ...package Component thermal solutions interface with the processor at the IHS surface Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC signal quality mechanical and thermal are satisfied Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows the operating system to reduce power consumption when performance is...

Page 11: ... processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks OEM Original Equipment Manufacturer 1 2 References Material and concepts available in the following documents may be beneficial when reading this doc...

Page 12: ...Introduction 12 Intel Xeon Processor 3500 Series Datasheet Volume 1 ...

Page 13: ...S pads associated with VCC 8 VTTA pads and 5 VSS pads associated with VTTA 28 VTTD pads and 17 VSS pads associated with VTTD 28 VDDQ pads and 17 VSS pads associated with VDDQ and 3 VCCPLL pads All VCCP VTTA VTTD VDDQ and VCCPLL lands must be connected to their respective processor power planes while all VSS lands must be connected to the system ground plane The processor VCC lands must be supplied...

Page 14: ...sor s maximum non turbo core frequency is configured during power on reset by using values stored internally during manufacturing The stored value sets the highest core multiplier at which the particular processor can operate If lower max non turbo speeds are desired the appropriate ratio can be configured via the CLOCK_FLEX_MAX MSR The processor uses differential clocks BCLK_DP BCLK_DN Clock mult...

Page 15: ...ID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1 04375 0 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1 03750 0 0 0 0 0 0 1 0 1 60000 0 1 0 1 1 1 0 1 1 03125 0 0 0 0 0 0 1 1 1 59375 0 1 0 1 1 1 1 0 1 02500 0 0 0 0 0 1 0 0 1 58750 0 1 0 1 1 1 1 1 1 01875 0 0 0 0 0 1 0 1 1 58125 0 1 1 0 0 0 0 0 1 01250 0 0 0 0 0 1 1 0 1 57500 0 1 1 0 0 0 0 1 1 00625 0 0 0 0 0 1 1 1 1...

Page 16: ... 0 71250 0 0 1 1 0 1 1 0 1 27500 1 0 0 1 0 0 0 1 0 70625 0 0 1 1 0 1 1 1 1 26875 1 0 0 1 0 0 1 0 0 70000 0 0 1 1 1 0 0 0 1 26250 1 0 0 1 0 0 1 1 0 69375 0 0 1 1 1 0 0 1 1 25625 1 0 0 1 0 1 0 0 0 68750 0 0 1 1 1 0 1 0 1 25000 1 0 0 1 0 1 0 1 0 68125 0 0 1 1 1 0 1 1 1 24375 1 0 0 1 0 1 1 0 0 67500 0 0 1 1 1 1 0 0 1 23750 1 0 0 1 0 1 1 1 0 66875 0 0 1 1 1 1 0 1 1 23125 1 0 0 1 1 0 0 0 0 66250 0 0 1 1...

Page 17: ...ing any signal to power or ground a resistor will also allow for system testability 0 1 0 0 1 1 1 1 1 11875 1 0 1 0 1 0 1 0 0 55000 0 1 0 1 0 0 0 0 1 11250 1 0 1 0 1 0 1 1 0 54375 0 1 0 1 0 0 0 1 1 10625 1 0 1 0 1 1 0 0 0 53750 0 1 0 1 0 0 1 0 1 10000 1 0 1 0 1 1 0 1 0 53125 0 1 0 1 0 0 1 1 1 09375 1 0 1 0 1 1 1 0 0 52500 0 1 0 1 0 1 0 0 1 08750 1 0 1 0 1 1 1 1 0 51875 0 1 0 1 0 1 0 1 1 08125 1 0 ...

Page 18: ...TX_DN DDR3 Reference Clocks Differential DDR3 Output DDR 0 1 2 _CLK D P 3 0 DDR3 Command Signals Single ended CMOS Output DDR 0 1 2 _RAS DDR 0 1 2 _CAS DDR 0 1 2 _WE DDR 0 1 2 _MA 15 0 DDR 0 1 2 _BA 2 0 Single ended Asynchronous Output DDR 0 1 2 _RESET DDR3 Control Signals Single ended CMOS Output DDR 0 1 2 _CS 5 4 DDR 0 1 2 _CS 1 0 DDR 0 1 2 _ODT 3 0 DDR 0 1 2 _CKE 3 0 DDR3 Data Signals Single en...

Page 19: ... Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two ...

Page 20: ...f DC electrical specifications shown in Table 2 5 is used with devices normally operating from a VTTD interface supply VTTD nominal levels will vary between processor families All PECI devices will operate at the VTTD level determined by the processor installed in the system For specific nominal VTTD levels refer to Table 2 7 Notes 1 VTTD supplies the PECI interface PECI behavior does not affect V...

Page 21: ...after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if ...

Page 22: ... 11 Control Sideband and Test Access Port TAP are listed in Table 2 12 through Table 2 15 Table 2 7 through Table 2 15 list the DC specifications for the processor and are valid only while meeting specifications for case temperature TCASE as specified in Chapter 6 Thermal Specifications clock frequency and input voltages Care should be taken to read all notes associated with each parameter Table 2...

Page 23: ...e less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 Refer to Table 2 8 and Figure 2 3 for the minimum typical and maximum VCC allowed for a given current The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current VTTA Voltage for the analog portion of the integrated memory controller Intel QPI...

Page 24: ... 035 VID 0 054 1 2 3 25 VID 0 020 VID 0 039 VID 0 058 1 2 3 30 VID 0 024 VID 0 043 VID 0 062 1 2 3 35 VID 0 028 VID 0 047 VID 0 066 1 2 3 40 VID 0 032 VID 0 051 VID 0 070 1 2 3 45 VID 0 036 VID 0 055 VID 0 074 1 2 3 50 VID 0 040 VID 0 059 VID 0 078 1 2 3 55 VID 0 044 VID 0 063 VID 0 082 1 2 3 60 VID 0 048 VID 0 067 VID 0 086 1 2 3 65 VID 0 052 VID 0 071 VID 0 090 1 2 3 70 VID 0 056 VID 0 075 VID 0...

Page 25: ... 1 0 1 120 V 0 1 0 1 0 1 1 0 1 095 V 0 1 0 1 1 0 1 0 1 070 V 0 1 0 1 1 1 1 0 1 045 V VID 0 000 VID 0 013 VID 0 025 VID 0 038 VID 0 050 VID 0 063 VID 0 075 VID 0 088 VID 0 100 VID 0 113 VID 0 125 VID 0 138 VID 0 150 VID 0 163 VID 0 175 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 V c c V Icc A Vcc Maximum Vcc Typical Vcc Minimum Table 2 10 VTT Static and Transient Tolerance Sheet 1 of 2 ITT A V...

Page 26: ... VID 0 0825 VID 0 1140 VID 0 1455 20 VID 0 0885 VID 0 1200 VID 0 1515 21 VID 0 0945 VID 0 1260 VID 0 1575 22 VID 0 1005 VID 0 1320 VID 0 1635 23 VID 0 1065 VID 0 1380 VID 0 1695 24 VID 0 1125 VID 0 1440 VID 0 1755 25 VID 0 1185 VID 0 1500 VID 0 1815 26 VID 0 1245 VID 0 1560 VID 0 1875 27 VID 0 1305 VID 0 1620 VID 0 1935 28 VID 0 1365 VID 0 1680 VID 0 1995 Notes 1 The ITT listed in this table is a ...

Page 27: ... V 2 4 VIH Input High Voltage 0 57 VDDQ V 3 VOL Output Low Voltage VDDQ 2 RON RON RVTT_TERM V VOH Output High Voltage VDDQ VDDQ 2 RON RON RVTT_TERM V 4 RON DDR3 Clock Buffer On Resistance 21 31 Ω RON DDR3 Command Buffer On Resistance 16 24 Ω RON DDR3 Reset Buffer On Resistance 25 75 Ω RON DDR3 Control Buffer On Resistance 21 31 Ω RON DDR3 Data Buffer On Resistance 21 31 Ω ILI Input Leakage Current...

Page 28: ...y to all processor frequencies 2 The VTTA referred to in these specifications refers to instantaneous VTTA 3 For Vin between 0 V and VTTA Measured when the driver is tristated 4 VIH and VOH may experience excursions above VTT 5 This spec applies to VCCPWRGOOD and VTTPWRGOOD 6 This specification applies to VDDPWRGOOD Table 2 12 RESET Signal DC Specifications Symbol Parameter Min Typ Max Units Notes...

Page 29: ...en transitioning from a high to low current load condition This overshoot cannot exceed VID VOS_MAX VOS_MAX is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands Table 2 15 Control Sideband Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage 0 64 VTTA V 2 V...

Page 30: ...Table 2 16 when measured across the VCC_SENSE and VSS_SENSE lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope Figure 2 5 VCC Overshoot Example Waveform Time Example Overshoot Waveform Voltage V VID VID VOS TOS VOS TOS Overshoot time above VID VOS Overshoot above VID ...

Page 31: ...eat Spreader IHS Thermal Interface Material TIM Processor core die Package substrate Capacitors Note 1 Socket and motherboard are included for reference and are not part of processor package 3 1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions i...

Page 32: ...Package Mechanical Specifications 32 Intel Xeon Processor 3500 Series Datasheet Volume 1 Figure 3 2 Processor Package Drawing Sheet 1 of 2 ...

Page 33: ...Intel Xeon Processor 3500 Series Datasheet Volume 1 33 Package Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 2 ...

Page 34: ...orm compressive loading in a direction normal to the processor IHS 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dy...

Page 35: ... 3 7 Processor Materials Table 3 3 lists some of the package components and associated materials 3 8 Processor Markings Figure 3 4 shows the topside markings on the processor This diagram is to aid in the identification of the processor Table 3 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Cop...

Page 36: ...ries Datasheet Volume 1 3 9 Processor Land Coordinates Figure 3 5 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Figure 3 5 Processor Land Coordinates and Quadrants Bottom View ...

Page 37: ...Xeon Processor 3500 Series Land Listing 4 1 Intel Xeon Processor 3500 Series Land Assignments This section provides sorted land list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor lands ordered alphabetically by land name Table 4 2 is a listing of all processor lands ordered by land number ...

Page 38: ...CLOCK O DDR0_CLK_P 2 F18 CLOCK O DDR0_CLK_P 3 E20 CLOCK O DDR0_CS 0 G15 CMOS O DDR0_CS 1 B10 CMOS O DDR0_CS 4 B15 CMOS O DDR0_CS 5 A7 CMOS O DDR0_DQ 0 W41 CMOS I O DDR0_DQ 1 V41 CMOS I O DDR0_DQ 10 K42 CMOS I O DDR0_DQ 11 K43 CMOS I O DDR0_DQ 12 P42 CMOS I O DDR0_DQ 13 P41 CMOS I O DDR0_DQ 14 L43 CMOS I O DDR0_DQ 15 L42 CMOS I O DDR0_DQ 16 H41 CMOS I O DDR0_DQ 17 H43 CMOS I O DDR0_DQ 18 E42 CMOS I...

Page 39: ...5 CMOS I O DDR0_DQS_P 0 T43 CMOS I O DDR0_DQS_P 1 L41 CMOS I O DDR0_DQS_P 2 F41 CMOS I O Table 4 1 Land Listing by Land Name Sheet 3 of 36 Land Name Land No Buffer Type Direction DDR0_DQS_P 3 B39 CMOS I O DDR0_DQS_P 4 E3 CMOS I O DDR0_DQS_P 5 K2 CMOS I O DDR0_DQS_P 6 R2 CMOS I O DDR0_DQS_P 7 W2 CMOS I O DDR0_DQS_P 8 D34 CMOS I O DDR0_ECC 0 C36 CMOS I O DDR0_ECC 1 A36 CMOS I O DDR0_ECC 2 F32 CMOS I...

Page 40: ...Q 25 L33 CMOS I O DDR1_DQ 26 K32 CMOS I O DDR1_DQ 27 J32 CMOS I O Table 4 1 Land Listing by Land Name Sheet 5 of 36 Land Name Land No Buffer Type Direction DDR1_DQ 28 J34 CMOS I O DDR1_DQ 29 H34 CMOS I O DDR1_DQ 3 Y34 CMOS I O DDR1_DQ 30 L32 CMOS I O DDR1_DQ 31 K30 CMOS I O DDR1_DQ 32 E9 CMOS I O DDR1_DQ 33 E8 CMOS I O DDR1_DQ 34 E5 CMOS I O DDR1_DQ 35 F5 CMOS I O DDR1_DQ 36 F10 CMOS I O DDR1_DQ 3...

Page 41: ...E24 CMOS O DDR1_MA 13 B14 CMOS O DDR1_MA 14 H26 CMOS O DDR1_MA 15 F26 CMOS O DDR1_MA 2 J17 CMOS O Table 4 1 Land Listing by Land Name Sheet 7 of 36 Land Name Land No Buffer Type Direction DDR1_MA 3 L28 CMOS O DDR1_MA 4 K28 CMOS O DDR1_MA 5 F22 CMOS O DDR1_MA 6 J27 CMOS O DDR1_MA 7 D22 CMOS O DDR1_MA 8 E22 CMOS O DDR1_MA 9 G24 CMOS O DDR1_ODT 0 D11 CMOS O DDR1_ODT 1 C8 CMOS O DDR1_ODT 2 D14 CMOS O ...

Page 42: ... I O DDR2_DQ 47 M8 CMOS I O DDR2_DQ 48 P7 CMOS I O Table 4 1 Land Listing by Land Name Sheet 9 of 36 Land Name Land No Buffer Type Direction DDR2_DQ 49 N6 CMOS I O DDR2_DQ 5 V34 CMOS I O DDR2_DQ 50 P9 CMOS I O DDR2_DQ 51 P10 CMOS I O DDR2_DQ 52 N8 CMOS I O DDR2_DQ 53 N7 CMOS I O DDR2_DQ 54 R10 CMOS I O DDR2_DQ 55 R9 CMOS I O DDR2_DQ 56 U5 CMOS I O DDR2_DQ 57 U6 CMOS I O DDR2_DQ 58 T10 CMOS I O DDR...

Page 43: ...e 4 1 Land Listing by Land Name Sheet 11 of 36 Land Name Land No Buffer Type Direction QPI_CLKTX_DN AF42 QPI O QPI_CLKTX_DP AG42 QPI O QPI_CMP 0 AL43 Analog QPI_DRX_DN 0 AU37 QPI I QPI_DRX_DN 1 AV38 QPI I QPI_DRX_DN 10 AT42 QPI I QPI_DRX_DN 11 AR43 QPI I QPI_DRX_DN 12 AR40 QPI I QPI_DRX_DN 13 AN42 QPI I QPI_DRX_DN 14 AM43 QPI I QPI_DRX_DN 15 AM40 QPI I QPI_DRX_DN 16 AM41 QPI I QPI_DRX_DN 17 AP40 Q...

Page 44: ... O QPI_DTX_DP 10 AF43 QPI O QPI_DTX_DP 11 AE42 QPI O QPI_DTX_DP 12 AD42 QPI O QPI_DTX_DP 13 AC43 QPI O QPI_DTX_DP 14 AD40 QPI O QPI_DTX_DP 15 AC41 QPI O QPI_DTX_DP 16 AC39 QPI O QPI_DTX_DP 17 AB39 QPI O QPI_DTX_DP 18 AD38 QPI O QPI_DTX_DP 19 AE40 QPI O QPI_DTX_DP 2 AK37 QPI O QPI_DTX_DP 3 AJ38 QPI O QPI_DTX_DP 4 AH40 QPI O Table 4 1 Land Listing by Land Name Sheet 13 of 36 Land Name Land No Buffer...

Page 45: ...T35 RSVD U40 RSVD M38 RSVD H38 RSVD H11 RSVD K9 RSVD N4 Table 4 1 Land Listing by Land Name Sheet 15 of 36 Land Name Land No Buffer Type Direction RSVD V6 RSVD H31 RSVD U35 RSVD B18 RSVD F21 RSVD J25 RSVD F23 RSVD A31 RSVD A40 RSVD AB3 RSVD AB6 RSVD AC3 RSVD AC4 RSVD AC6 RSVD AC8 RSVD AD1 RSVD AD2 RSVD AD3 RSVD AD4 RSVD AD5 RSVD AD6 RSVD AD7 RSVD AD8 RSVD AE1 RSVD AE3 RSVD AE4 RSVD AE5 RSVD AE6 RS...

Page 46: ...AM36 RSVD AM38 RSVD AM4 RSVD AM6 RSVD AM7 RSVD AM8 RSVD AN1 Table 4 1 Land Listing by Land Name Sheet 17 of 36 Land Name Land No Buffer Type Direction RSVD AN2 RSVD AN36 RSVD AN38 RSVD AN4 RSVD AN5 RSVD AN6 RSVD AP2 RSVD AP3 RSVD AP4 RSVD AR1 RSVD AR36 RSVD AR37 RSVD AR4 RSVD AR5 RSVD AR6 RSVD AT1 RSVD AT2 RSVD AT3 RSVD AT36 RSVD AT4 RSVD AT5 RSVD AT6 RSVD AU2 RSVD AU3 RSVD AU4 RSVD AU6 RSVD AU7 R...

Page 47: ... Land Name Sheet 19 of 36 Land Name Land No Buffer Type Direction SKTOCC AG36 GTL O TCK AH10 TAP I TDI AJ9 TAP I TDO AJ10 TAP O THERMTRIP AG37 GTL O TMS AG10 TAP I TRST AH9 TAP I VCC AH11 PWR VCC AH33 PWR VCC AJ11 PWR VCC AJ33 PWR VCC AK11 PWR VCC AK12 PWR VCC AK13 PWR VCC AK15 PWR VCC AK16 PWR VCC AK18 PWR VCC AK19 PWR VCC AK21 PWR VCC AK24 PWR VCC AK25 PWR VCC AK27 PWR VCC AK28 PWR VCC AK30 PWR ...

Page 48: ...AP15 PWR VCC AP16 PWR VCC AP18 PWR VCC AP19 PWR VCC AP21 PWR Table 4 1 Land Listing by Land Name Sheet 21 of 36 Land Name Land No Buffer Type Direction VCC AP24 PWR VCC AP25 PWR VCC AP27 PWR VCC AP28 PWR VCC AP30 PWR VCC AP31 PWR VCC AP33 PWR VCC AP34 PWR VCC AR10 PWR VCC AR12 PWR VCC AR13 PWR VCC AR15 PWR VCC AR16 PWR VCC AR18 PWR VCC AR19 PWR VCC AR21 PWR VCC AR24 PWR VCC AR25 PWR VCC AR27 PWR V...

Page 49: ...AV34 PWR VCC AV9 PWR VCC AW10 PWR VCC AW12 PWR VCC AW13 PWR Table 4 1 Land Listing by Land Name Sheet 23 of 36 Land Name Land No Buffer Type Direction VCC AW15 PWR VCC AW16 PWR VCC AW18 PWR VCC AW19 PWR VCC AW21 PWR VCC AW24 PWR VCC AW25 PWR VCC AW27 PWR VCC AW28 PWR VCC AW30 PWR VCC AW31 PWR VCC AW33 PWR VCC AW34 PWR VCC AW9 PWR VCC AY10 PWR VCC AY12 PWR VCC AY13 PWR VCC AY15 PWR VCC AY16 PWR VCC...

Page 50: ...DQ B27 PWR VDDQ B32 PWR VDDQ B7 PWR Table 4 1 Land Listing by Land Name Sheet 25 of 36 Land Name Land No Buffer Type Direction VDDQ C10 PWR VDDQ C15 PWR VDDQ C20 PWR VDDQ C25 PWR VDDQ C30 PWR VDDQ D13 PWR VDDQ D18 PWR VDDQ D23 PWR VDDQ D28 PWR VDDQ E11 PWR VDDQ E16 PWR VDDQ E21 PWR VDDQ E26 PWR VDDQ E31 PWR VDDQ F14 PWR VDDQ F19 PWR VDDQ F24 PWR VDDQ G17 PWR VDDQ G22 PWR VDDQ G27 PWR VDDQ H15 PWR ...

Page 51: ...D VSS AF5 GND VSS AG11 GND VSS AG3 GND VSS AG33 GND VSS AG43 GND Table 4 1 Land Listing by Land Name Sheet 27 of 36 Land Name Land No Buffer Type Direction VSS AG9 GND VSS AH1 GND VSS AH34 GND VSS AH37 GND VSS AH39 GND VSS AH7 GND VSS AJ34 GND VSS AJ36 GND VSS AJ41 GND VSS AJ5 GND VSS AK10 GND VSS AK14 GND VSS AK17 GND VSS AK20 GND VSS AK22 GND VSS AK23 GND VSS AK26 GND VSS AK29 GND VSS AK3 GND VS...

Page 52: ...AP20 GND VSS AP22 GND VSS AP23 GND VSS AP26 GND VSS AP29 GND Table 4 1 Land Listing by Land Name Sheet 29 of 36 Land Name Land No Buffer Type Direction VSS AP32 GND VSS AP35 GND VSS AP36 GND VSS AP37 GND VSS AP43 GND VSS AP5 GND VSS AP6 GND VSS AR11 GND VSS AR14 GND VSS AR17 GND VSS AR2 GND VSS AR20 GND VSS AR22 GND VSS AR23 GND VSS AR26 GND VSS AR29 GND VSS AR3 GND VSS AR32 GND VSS AR35 GND VSS A...

Page 53: ...S AW8 GND VSS AY11 GND VSS AY14 GND VSS AY17 GND VSS AY2 GND VSS AY20 GND Table 4 1 Land Listing by Land Name Sheet 31 of 36 Land Name Land No Buffer Type Direction VSS AY22 GND VSS AY23 GND VSS AY26 GND VSS AY29 GND VSS AY32 GND VSS AY37 GND VSS AY42 GND VSS AY7 GND VSS B2 GND VSS B37 GND VSS B42 GND VSS BA11 GND VSS BA14 GND VSS BA17 GND VSS BA20 GND VSS BA26 GND VSS BA29 GND VSS BA3 GND VSS BA3...

Page 54: ...ND VSS M22 GND VSS M24 GND VSS M26 GND VSS M28 GND VSS M30 GND Table 4 1 Land Listing by Land Name Sheet 33 of 36 Land Name Land No Buffer Type Direction VSS M32 GND VSS M37 GND VSS M42 GND VSS M7 GND VSS N10 GND VSS N35 GND VSS N40 GND VSS N5 GND VSS P11 GND VSS P3 GND VSS P33 GND VSS P38 GND VSS P43 GND VSS P8 GND VSS R1 GND VSS R36 GND VSS R41 GND VSS R6 GND VSS T34 GND VSS T39 GND VSS T4 GND V...

Page 55: ... AA10 PWR VTTD AA11 PWR VTTD AA33 PWR VTTD AB10 PWR VTTD AB11 PWR VTTD AB33 PWR Table 4 1 Land Listing by Land Name Sheet 35 of 36 Land Name Land No Buffer Type Direction VTTD AB34 PWR VTTD AB8 PWR VTTD AB9 PWR VTTD AC10 PWR VTTD AC11 PWR VTTD AC33 PWR VTTD AC34 PWR VTTD AC35 PWR VTTD AD34 PWR VTTD AD35 PWR VTTD AD36 PWR VTTD AD9 PWR VTTD AE34 PWR VTTD AE35 PWR VTTD AE8 PWR VTTD AE9 PWR VTTD AF36 ...

Page 56: ...MOS O A8 DDR1_CS 1 CMOS O A9 VDDQ PWR AA10 VTTD PWR AA11 VTTD PWR AA3 VSS GND AA33 VTTD PWR AA34 VSS GND AA35 DDR1_DQ 4 CMOS I O AA36 DDR1_DQ 1 CMOS I O AA37 DDR1_DQ 0 CMOS I O AA38 VSS GND AA39 VSS GND AA4 BCLK_ITP_DN CMOS O AA40 RSVD AA41 RSVD AA5 BCLK_ITP_DP CMOS O AA6 VDDPWRGOOD Asynch I AA7 DDR1_DQ 62 CMOS I O AA8 DDR_COMP 0 Analog AA9 VSS GND AB10 VTTD PWR AB11 VTTD PWR AB3 RSVD AB33 VTTD PW...

Page 57: ...1 RSVD AE10 VTTA PWR AE11 VTTA PWR AE2 VSS GND Table 4 2 Land Listing by Land Number Sheet 3 of 36 Land No Pin Name Buffer Type Direction AE3 RSVD AE33 VTTA PWR AE34 VTTD PWR AE35 VTTD PWR AE36 VTT_SENSE Analog AE37 VSS_SENSE_VTT Analog AE38 QPI_DTX_DN 18 QPI O AE39 VSS GND AE4 RSVD AE40 QPI_DTX_DP 19 QPI O AE41 QPI_DTX_DN 11 QPI O AE42 QPI_DTX_DP 11 QPI O AE43 QPI_DTX_DN 10 QPI O AE5 RSVD AE6 RSV...

Page 58: ...AH39 VSS GND AH4 RSVD AH40 QPI_DTX_DP 4 QPI O AH41 QPI_DTX_DP 6 QPI O AH42 QPI_DTX_DN 6 QPI O Table 4 2 Land Listing by Land Number Sheet 5 of 36 Land No Pin Name Buffer Type Direction AH43 QPI_DTX_DN 8 QPI O AH5 FC_AH5 AH6 RSVD AH7 VSS GND AH8 RSVD AH9 TRST TAP I AJ1 RSVD AJ10 TDO TAP O AJ11 VCC PWR AJ2 RSVD AJ3 RSVD AJ33 VCC PWR AJ34 VSS GND AJ35 BCLK_DP CMOS I AJ36 VSS GND AJ37 RSVD AJ38 QPI_DT...

Page 59: ...MSID 0 CMOS I O AL11 VSS GND AL12 VCC PWR AL13 VCC PWR AL14 VSS GND AL15 VCC PWR Table 4 2 Land Listing by Land Number Sheet 7 of 36 Land No Pin Name Buffer Type Direction AL16 VCC PWR AL17 VSS GND AL18 VCC PWR AL19 VCC PWR AL2 VSS GND AL20 VSS GND AL21 VCC PWR AL22 VSS GND AL23 VSS GND AL24 VCC PWR AL25 VCC PWR AL26 VSS GND AL27 VCC PWR AL28 VCC PWR AL29 VSS GND AL3 RSVD AL30 VCC PWR AL31 VCC PWR...

Page 60: ...14 QPI I AM5 VSS GND AM6 RSVD AM7 RSVD AM8 RSVD Table 4 2 Land Listing by Land Number Sheet 9 of 36 Land No Pin Name Buffer Type Direction AM9 VSS GND AN1 RSVD AN10 VID 4 CSC 1 CMOS I O AN11 VSS GND AN12 VCC PWR AN13 VCC PWR AN14 VSS GND AN15 VCC PWR AN16 VCC PWR AN17 VSS GND AN18 VCC PWR AN19 VCC PWR AN2 RSVD AN20 VSS GND AN21 VCC PWR AN22 VSS GND AN23 VSS GND AN24 VCC PWR AN25 VCC PWR AN26 VSS G...

Page 61: ...X_DP 19 QPI I AP39 QPI_DRX_DN 18 QPI I AP4 RSVD Table 4 2 Land Listing by Land Number Sheet 11 of 36 Land No Pin Name Buffer Type Direction AP40 QPI_DRX_DN 17 QPI I AP41 QPI_DRX_DP 17 QPI I AP42 QPI_DRX_DP 13 QPI I AP43 VSS GND AP5 VSS GND AP6 VSS GND AP7 PSI CMOS O AP8 VID 6 CMOS O AP9 VID 5 CSC 2 CMOS I O AR1 RSVD AR10 VCC PWR AR11 VSS GND AR12 VCC PWR AR13 VCC PWR AR14 VSS GND AR15 VCC PWR AR16...

Page 62: ...8 VCC PWR AT29 VSS GND AT3 RSVD AT30 VCC PWR AT31 VCC PWR AT32 VSS GND Table 4 2 Land Listing by Land Number Sheet 13 of 36 Land No Pin Name Buffer Type Direction AT33 VCC PWR AT34 VCC PWR AT35 VSS GND AT36 RSVD AT37 QPI_DRX_DP 0 QPI I AT38 VSS GND AT39 QPI_DRX_DN 7 QPI I AT4 RSVD AT40 QPI_DRX_DP 12 QPI I AT41 VSS GND AT42 QPI_DRX_DN 10 QPI I AT43 QPI_DRX_DP 11 QPI I AT5 RSVD AT6 RSVD AT7 VSS GND ...

Page 63: ...21 VCC PWR AV22 VSS GND AV23 VSS GND AV24 VCC PWR AV25 VCC PWR Table 4 2 Land Listing by Land Number Sheet 15 of 36 Land No Pin Name Buffer Type Direction AV26 VSS GND AV27 VCC PWR AV28 VCC PWR AV29 VSS GND AV3 VTT_VID2 CMOS O AV30 VCC PWR AV31 VCC PWR AV32 VSS GND AV33 VCC PWR AV34 VCC PWR AV35 RSVD AV36 QPI_DRX_DP 2 QPI I AV37 QPI_DRX_DN 2 QPI I AV38 QPI_DRX_DN 1 QPI I AV39 VSS GND AV4 VSS GND A...

Page 64: ...AY17 VSS GND AY18 VCC PWR AY19 VCC PWR AY2 VSS GND Table 4 2 Land Listing by Land Number Sheet 17 of 36 Land No Pin Name Buffer Type Direction AY20 VSS GND AY21 VCC PWR AY22 VSS GND AY23 VSS GND AY24 VCC PWR AY25 VCC PWR AY26 VSS GND AY27 VCC PWR AY28 VCC PWR AY29 VSS GND AY3 RSVD AY30 VCC PWR AY31 VCC PWR AY32 VSS GND AY33 VCC PWR AY34 VCC PWR AY35 RSVD AY36 QPI_DRX_DN 3 QPI I AY37 VSS GND AY38 Q...

Page 65: ... B9 RSVD BA10 VCC PWR BA11 VSS GND BA12 VCC PWR BA13 VCC PWR BA14 VSS GND BA15 VCC PWR Table 4 2 Land Listing by Land Number Sheet 19 of 36 Land No Pin Name Buffer Type Direction BA16 VCC PWR BA17 VSS GND BA18 VCC PWR BA19 VCC PWR BA20 VSS GND BA24 VCC PWR BA25 VCC PWR BA26 VSS GND BA27 VCC PWR BA28 VCC PWR BA29 VSS GND BA3 VSS GND BA30 VCC PWR BA35 VSS GND BA36 QPI_DRX_DP 4 QPI I BA37 QPI_DRX_DN ...

Page 66: ...MOS O D15 DDR2_ODT 2 CMOS O D16 RSVD D17 DDR2_RAS CMOS O D18 VDDQ PWR D19 DDR0_CLK_P 1 CLOCK O Table 4 2 Land Listing by Land Number Sheet 21 of 36 Land No Pin Name Buffer Type Direction D2 BPM 6 GTL I O D20 RSVD D21 DDR1_CLK_N 0 CLOCK O D22 DDR1_MA 7 CMOS O D23 VDDQ PWR D24 DDR0_MA 3 CMOS O D25 RSVD D26 DDR2_CKE 2 CMOS O D27 DDR1_CKE 2 CMOS O D28 VDDQ PWR D29 DDR1_RESET CMOS O D3 VSS GND D30 RSVD...

Page 67: ...CMOS I O E9 DDR1_DQ 32 CMOS I O F1 DDR0_DQ 34 CMOS I O F10 DDR1_DQ 36 CMOS I O F11 DDR1_ODT 3 CMOS O Table 4 2 Land Listing by Land Number Sheet 23 of 36 Land No Pin Name Buffer Type Direction F12 DDR0_ODT 0 CMOS O F13 DDR2_ODT 1 CMOS O F14 VDDQ PWR F15 DDR2_MA 13 CMOS O F16 DDR2_CAS CMOS O F17 DDR2_BA 1 CMOS O F18 DDR0_CLK_P 2 CLOCK O F19 VDDQ PWR F2 DDR0_DQ 39 CMOS I O F20 DDR2_MA 4 CMOS O F21 R...

Page 68: ... CMOS I O G41 DDR0_DQS_N 2 CMOS I O G42 VSS GND G43 RSVD Table 4 2 Land Listing by Land Number Sheet 25 of 36 Land No Pin Name Buffer Type Direction G5 DDR1_DQ 46 CMOS I O G6 DDR1_DQS_N 5 CMOS I O G7 VSS GND G8 DDR1_DQ 37 CMOS I O G9 DDR1_DQ 44 CMOS I O H1 DDR0_DQ 41 CMOS I O H10 VSS GND H11 RSVD H12 DDR2_DQ 38 CMOS I O H13 DDR2_DQ 34 CMOS I O H14 DDR1_MA 10 CMOS O H15 VDDQ PWR H16 RSVD H17 DDR2_M...

Page 69: ... J35 DDR1_DQ 19 CMOS I O J36 DDR1_DQ 22 CMOS I O Table 4 2 Land Listing by Land Number Sheet 27 of 36 Land No Pin Name Buffer Type Direction J37 DDR2_DQ 26 CMOS I O J38 VSS GND J39 DDR2_DQ 19 CMOS I O J4 DDR1_DQ 52 CMOS I O J40 DDR2_DQ 18 CMOS I O J41 DDR0_DQ 21 CMOS I O J42 DDR0_DQ 20 CMOS I O J43 VSS GND J5 DDR1_DQ 47 CMOS I O J6 DDR1_DQ 41 CMOS I O J7 RSVD J8 VSS GND J9 DDR2_DQS_N 4 CMOS I O K1...

Page 70: ...R2_MA 8 CMOS O L26 DDR2_BA 2 CMOS O L27 DDR2_CKE 3 CMOS O L28 DDR1_MA 3 CMOS O L29 VSS GND Table 4 2 Land Listing by Land Number Sheet 29 of 36 Land No Pin Name Buffer Type Direction L3 DDR0_DQ 46 CMOS I O L30 DDR1_DQS_P 3 CMOS I O L31 DDR1_DQS_N 3 CMOS I O L32 DDR1_DQ 30 CMOS I O L33 DDR1_DQ 25 CMOS I O L34 VSS GND L35 DDR1_DQS_P 2 CMOS I O L36 DDR1_DQS_N 2 CMOS I O L37 RSVD L38 RSVD L39 VSS GND ...

Page 71: ...DDR1_DQ 11 CMOS I O N4 RSVD N40 VSS GND Table 4 2 Land Listing by Land Number Sheet 31 of 36 Land No Pin Name Buffer Type Direction N41 DDR0_DQ 8 CMOS I O N42 RSVD N43 DDR0_DQ 9 CMOS I O N5 VSS GND N6 DDR2_DQ 49 CMOS I O N7 DDR2_DQ 53 CMOS I O N8 DDR2_DQ 52 CMOS I O N9 DDR2_DQ 43 CMOS I O P1 RSVD P10 DDR2_DQ 51 CMOS I O P11 VSS GND P2 RSVD P3 VSS GND P33 VSS GND P34 DDR1_DQ 8 CMOS I O P35 DDR1_DQ ...

Page 72: ... I O T8 DDR2_DQS_N 7 CMOS I O T9 VSS GND U1 DDR0_DQ 60 CMOS I O U10 DDR2_DQ 59 CMOS I O U11 RSVD U2 VSS GND Table 4 2 Land Listing by Land Number Sheet 33 of 36 Land No Pin Name Buffer Type Direction U3 DDR0_DQ 61 CMOS I O U33 VCCPLL PWR U34 DDR2_DQ 4 CMOS I O U35 RSVD U36 DDR2_DQ 3 CMOS I O U37 VSS GND U38 DDR2_DQ 8 CMOS I O U39 DDR2_DQ 9 CMOS I O U4 DDR0_DQ 56 CMOS I O U40 RSVD U41 DDR0_DQ 6 CMO...

Page 73: ... VSS GND W5 DDR1_DQ 61 CMOS I O W6 DDR1_DQ 56 CMOS I O W7 DDR1_DQ 57 CMOS I O W8 VSS GND W9 DDR1_DQ 63 CMOS I O Table 4 2 Land Listing by Land Number Sheet 35 of 36 Land No Pin Name Buffer Type Direction Y1 VSS GND Y10 DDR1_DQ 58 CMOS I O Y11 VSS GND Y2 DDR0_DQ 58 CMOS I O Y3 DDR0_DQ 59 CMOS I O Y33 VSS GND Y34 DDR1_DQ 3 CMOS I O Y35 DDR1_DQ 2 CMOS I O Y36 VSS GND Y37 DDR1_DQS_N 0 CMOS I O Y38 DDR...

Page 74: ...Intel Xeon Processor 3500 Series Land Listing 74 Intel Xeon Processor 3500 Series Datasheet Volume 1 ...

Page 75: ...tor QPI_DRX_DN 19 0 QPI_DRX_DP 19 0 I I QPI_DRX_DN 19 0 and QPI_DRX_DP 19 0 comprise the differential receive data for the QPI port The inbound 20 lanes are connected to another component s outbound direction QPI_DTX_DN 19 0 QPI_DTX_DP 19 0 O O QPI_DTX_DN 19 0 and QPIQPI_DTX_DP 19 0 comprise the differential transmit data for the QPI port The outbound 20 lanes are connected to another component s ...

Page 76: ...ve on die termination and must be terminated on the system board PSI O Processor Power Status Indicator signal This signal is asserted when maximum possible processor core current consumption is less than 20A Assertion of this signal is an indication that the VR controller does not currently need to be able to provide ICC above 20A and the VR controller can use this information to move to more eff...

Page 77: ...st again be stable before a subsequent rising edge of VCCPWRGOOD In addition at the time VCCPWRGOOD is asserted RESET must be active The PWRGOOD signal must be supplied to the processor It should be driven high throughout boundary scan operation VDDPWRGOOD I VDDPWRGOOD is an input that indicates the VDDQ power supply is good The processor requires this signal to be a clean indication that the VDDQ...

Page 78: ...ocessor requires this input signal to be a clean indication that the VTT power supply is stable and within specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Note that it is not valid for...

Page 79: ...s verified compliant to the processor case temperature thermal profile at the customer defined boundary conditions is expected to be compliant with this update No redesign of the thermal solution should be necessary A fan speed control algorithms that was compliant to the previous thermal requirements is also expected to be compliant with this specification The fan speed control algorithm can be u...

Page 80: ...iate processor Thermal and Mechanical Design Guide see Section 1 2 for details on system thermal solution design thermal profiles and environmental considerations Notes 1 These values are specified at VCC_MAX for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC Refer ...

Page 81: ...0 TTV Power W TTV Tcase in C y 43 2 0 19 P Table 6 2 Processor Thermal Profile Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C 0 43 2 34 49 7 68 56 1 100 62 2 2 43 6 36 50 0 70 56 5 102 62 6 4 44 0 38 50 4 72 56 9 104 63 0 6 44 3 40 50 8 74 57 3 106 63 3 8 44 7 42 51 2 76 57 6 108 63 7 10 45 1 44 51 6 78 58 0 110 64 1 12 45 5 46 51 9 80 58 4 112 64 5 14 45 9 48 52 3...

Page 82: ...chanical Design Guidelines see Section 1 2 for details on characterizing the fan speed to ΨCA and ambient temperature measurement Notes 1 The ambient temperature is measured at the inlet to the processor thermal solution 2 This column can be expressed as a function of TAMBIENT by the following equation YCA 0 19 43 2 TAMBIENT 0 013 3 This column can be expressed as a function of TAMBIENT by the fol...

Page 83: ...rature measurement methodology and attaching the thermocouple refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Notes 1 Figure is not to scale and is for reference only 2 B1 Max 45 07 mm Min 44 93 mm 3 B2 Max 42 57 mm Min 42 43 mm 4 C1 Max 39 1 mm Min 38 9 mm 5 C2 Max 36 6 mm Min 36 4 mm 6 C3 Max 2 3 mm Min 2 2 mm 7 C4 Max 2 3 mm Min 2 2 mm 8 Refer to the ...

Page 84: ...ious generation processors reduces power consumption by modulating starting and stopping the internal processor core clocks The processor intelligently selects the appropriate TCC method to use on a dynamic basis BIOS is not required to select a specific method as with previous generation processors supporting TM1 or TM2 The temperature at which Adaptive Thermal Monitor activates the Thermal Contr...

Page 85: ...at the lower frequency and voltage will reduce power consumption and should allow the processor to cool off If after 1ms the processor is still too hot the temperature has not dropped below the TCC activation point DTS still 0 and PROCHOT is still active then a second frequency and voltage transition will take place This sequence of temperature checking and Frequency VID reduction will continue un...

Page 86: ...mperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases 6 2 2 3 Immediate Transiton to combined TM1 and TM2 As mentioned above when the TCC is activated the processor will sequentially step down the ratio multipliers and VIDs in an attempt to reduce the silicon temperature If the tempe...

Page 87: ...it may be configured as bi directional When configured in bi directional mode it is either an output indicating the processor has exceeded its TCC activation temperature or it can be driven from an external source for example a voltage regulator to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components As an output PROCHOT Proce...

Page 88: ... reliability to transfer critical device operating conditions and configuration information 6 3 1 1 Fan Speed Control with Digital Thermal Sensor Fan speed control solutions use a value stored in the static variable TCONTROL The DTS temperature data which is delivered over PECI in response to a GetTemp0 command is compared to this TCONTROL reference The DTS temperature is reported as a relative va...

Page 89: ...y the system designers Of course fan control chips can also monitor the Prochot pin to detect TCC activation via a dedicated input pin on the package Further details on how the Thermal Averaging Constant influences the fractional temperature values are available in the Thermal Design Guide 6 3 2 PECI Specifications 6 3 2 1 PECI Device Address The PECI register resides at address 30h 6 3 2 2 PECI C...

Page 90: ...ns outside sustained limits but within absolute maximum and minimum ratings quality reliability may be affected Notes 1 Refers to a component device that is not assembled in a board or socket that is not to be electrically connected to a voltage reference or I O signals 2 Specified temperatures are based on data collected Exceptions for surface mount reflow are specified in by applicable JEDEC sta...

Page 91: ...e level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 6 Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by TSUSTAINED and customer shelf life in applicable intel box and bags ...

Page 92: ...Thermal Specifications 92 Intel Xeon Processor 3500 Series Datasheet Volume 1 ...

Page 93: ...ds are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads to the system The P_LVLx I O Monitor address does not need to be set up before using the P_LVLx I O read interface Software may make C state requests by using a legacy method involving I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This feature...

Page 94: ...te was entered via the MWAIT instruction RESET will cause the processor to initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the C1 state See the Intel 64 and IA 32 Architectures Software Developer s Manuals Volume III System Programmer s Guide for more information Figure 7 1 Power States C0 1 No transition to C0 is needed to service a snoo...

Page 95: ...ally resolved by the processor depending on the core power states and permission from the rest of the system as described in the following sections 7 2 2 1 Package C0 State This is the normal operating state for the processor The processor remains in the Normal state when at least one of its cores is in the C0 or C1 state or when another component in the system has not granted permission to the pr...

Page 96: ...tions are coordinated by the processor in response PM Request PMReq messages from the chipset The processor itself will never request a particular S state Notes 1 If the chipset requests an S state transition which is not allowed a machine check error will be generated by the processor 7 4 ACPI P States Intel Turbo Boost Technology The processor supports ACPI P States A new feature is that the P0 ...

Page 97: ... VCC is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism Software transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transit...

Page 98: ...Features 98 Intel Xeon Processor 3500 Series Datasheet Volume 1 ...

Page 99: ... figures in this chapter are dimensioned in millimeters and inches in brackets Figure 8 1 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprie...

Page 100: ...red around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 8 2 Side View and Figure 8 3 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure...

Page 101: ...or Specifications Notes 1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Figure 8 3 Space Requirements for the Boxed Processor top view Figure 8 4 Space Requirements for the Boxed Processor overall view ...

Page 102: ...tputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides VOH to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The fan heatsink receives a PWM signal from the motherboar...

Page 103: ... the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 8 7 and Figure 8 8 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the ...

Page 104: ...ications 104 Intel Xeon Processor 3500 Series Datasheet Volume 1 Figure 8 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements top view Figure 8 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements side view ...

Page 105: ... Table 8 2 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 40 ºC Meeting the processor s temperature specification see Chapter 6 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor Refer...

Page 106: ...s is achieved by more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors DTS and PECI Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures I...

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