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Connections

Intel® SHG2 DP Server Board Technical Product Specification

Intel Order Number C11343-001

Revision 1.0

Pin

Name

Internal USB Connector

8 USBP3_GND

9 Key

Reserved for future use

8.10.2

Mouse and Keyboard Ports

[Key-D & E]

Two identical PS/2 compatible ports share a common stacked housing. The top

PS/2 connector is labeled "mouse" and the bottom connector is labeled "keyboard," although
the SHG2 server board will support swapping these connections.

Table 50. Mouse and Keyboard Ports

[Key-D & E]

Mouse

Mouse / Keyboard Connector

Keyboard

Pin Signal Description

Pin Signal

Description

MSDATA

Mouse Data

KBDATA

Keyboard Data

2 GND

Ground

2 GND

Ground

3 GND

Ground

3 GND

Ground

4 MSFUSE

+5V

4 KBFUSE

+5V

MSCLK

Mouse clock

KBCLK

Keyboard clock

6 GND

Ground

6 GND Ground

8.10.3 Serial

Ports

[Key-F & L]

The SHG2 server board provides one RS-232C serial port and a second serial

port available through an onboard header [Key L]. The back panel serial port is a D-
subminiature 9-pin connector.

Table 51. Serial A Port Connector

[Key-F]

Pin

Signal

Serial Port Connector

00_1 (carrier detect)

SIORXD – 00_1 (receive data)

SIOTXD – 00_1 (transmit data)

00_1 (data terminal ready)

5 GROUND

00_1 (data set ready)

00_1 (request to send)

00_1 (clear to send)

SIORI + 00_1 (ring indicator)

Summary of Contents for SHG2 DP

Page 1: ...Intel Order Number C11343 001 Intel SHG2 DP Server Board Technical Product Specification Intel Order Number C11343 001 Revision 1 0 June 2002 Enterprise Platforms and Services Division ...

Page 2: ...tual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice The Intel SHG2 Server Board may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata will be availa...

Page 3: ...ermination Regulation Power 7 2 2 2 Miscellaneous Processor Subsystem Logic 7 2 2 3 Server Management Registers and Sensors 7 2 2 4 ServerWorks Grand Champion LE Chipset 8 2 2 5 CMIC LE 8 2 3 Memory Subsystem 9 2 3 1 Chipkill 9 2 3 2 Memory Configuration 9 2 3 3 CIOB X2 11 2 4 CSB5 South Bridge 11 2 4 1 PCI Interface 12 2 4 2 PCI Bus Master IDE Interface 12 2 4 3 USB Interface 12 2 4 4 BIOS Flash ...

Page 4: ...ntroller 19 3 3 64 bit 133MHz PCI X Subsystem 19 3 3 1 Device IDs IDSEL 19 3 3 2 64 133MHz Segment Arbitration 19 3 3 3 Ultra 160 SCSI Controller Adaptec AIC 7899 20 3 4 Modular RAID Capable PCI Slot 6 20 3 5 32 bit 33 MHz PCI Subsystem 20 3 5 1 Device IDs IDSEL 21 3 5 2 32 33 MHz PCI Arbitration 21 3 5 3 Network Interface Controller NIC 21 3 5 4 Video Controller 22 3 6 Interrupt Routing 23 3 6 1 ...

Page 5: ...nventions 35 6 3 System Management Interrupt SMI Handler 37 6 3 1 PCI Bus Error 37 6 3 2 Intel Xeon Processor Bus Error 37 6 3 3 Memory Bus Error 37 6 3 4 System Limit Error 37 6 3 5 Processor Failure 37 6 3 6 Boot Event 38 6 3 7 Chip Set Failure 38 6 4 Firmware BMC 38 6 4 1 System Event Log SEL Full 38 6 4 2 Timestamp Clock 38 6 4 3 Fault Resilient Booting 38 6 5 Error Messages and Error Codes 39...

Page 6: ...el Interface 55 8 7 Processor Connector 56 8 8 System Management Interfaces 60 8 8 1 ICMB Connector 60 8 8 2 Auxiliary I2C Connector 60 8 9 Baseboard Fan Connectors 61 8 9 1 Fan Connector Pin out 63 8 10 Standard I O Panel Connectors 64 8 10 1 Universal Serial Bus USB Interface 65 8 10 2 Mouse and Keyboard Ports 66 8 10 3 Serial Ports 66 8 10 4 Parallel Port 67 8 10 5 Video Port 68 8 10 6 Ethernet...

Page 7: ...ormation 80 11 1 Product Regulatory Compliance 80 11 1 1 Product Safety Compliance 80 11 1 2 Product EMC Compliance 80 11 1 3 Product Regulatory Compliance Markings 80 11 2 Electromagnetic Compatibility Notices 80 11 2 1 Europe CE Declaration of Conformity 80 11 2 2 Australian Communications Authority ACA C Tick Declaration of Conformity 81 11 2 3 Ministry of Economic Development New Zealand Decla...

Page 8: ...d Clock Distribution 28 Figure 7 SHG2 Sahalee BMC Block Diagram 29 Figure 8 Basic Reset Flow 32 Figure 9 Jumper Location 48 Figure 10 SHG2 Baseboard Connector Identification and Locations 50 Figure 11 SHG2 Board Fan Connector Locations 61 Figure 12 SHG2 System Redundant Cooling Fan Support 62 Figure 13 SHG2 I O Panel Connector Graphical Locations 64 Figure 14 SHG2 I O Panel Connector Location Dime...

Page 9: ...4 133MHz Segment Configuration IDs 19 Table 13 64 133 MHz Segment Arbitration Connections 20 Table 14 32 33MHz Segment Configuration IDs 21 Table 15 32 33MHz Segment Arbitration Connections 21 Table 16 Standard VGA Modes 22 Table 17 Video Port Connector Pinout 23 Table 18 ADM1026 Input Definition 30 Table 19 Temperature Sensors 31 Table 20 IPMB Bus Devices 33 Table 21 Private I2 C Bus 1 Devices 33...

Page 10: ...ble 43 ICMB Connector Pin out 60 Table 44 IPMB Connector Pinout 60 Table 45 SC5200 Fan Implementation 63 Table 46 Fan Connector Pinout 63 Table 47 I O Panel Connectors 65 Table 48 USB Connector 65 Table 49 Internal USB Connector 65 Table 50 Mouse and Keyboard Ports 66 Table 51 Serial A Port Connector 66 Table 52 Serial B Port Header COM2 EMP 67 Table 53 Parallel Port Connector 67 Table 54 Video Co...

Page 11: ...Product Specification List of Tables Revision 1 0 Intel Order Number C11343 001 xi Table 64 SHG2 Ripple and Noise Specification 74 Table 65 Voltage Timing Parameters 74 Table 66 Turn On Off Timing 75 Table 67 Transient Load Requirements 77 ...

Page 12: ...List of Tables Intel SHG2 DP Server Board Technical Product Specification Intel Order Number C11343 001 Revision 1 0 xii This page intentionally left blank ...

Page 13: ... Prestonia Processor PCI X 133 DDR 200 CHA FSB PCI 64 PCI 64 G bit LAN PCI 64 CSB5 IDE Flash ATA 100 IDE ATA 100 Video PCI 32 33 PCI 32 PCI 32 Thin IM B Video Conn LPC Rear USB USB 1 1 Rear USB USB 1 1 X BUS BM C SIO Serial Ports PS 2 Parallel Floppy PCI 32 DIM M DIM M DIM M DIM M DIM M DIM M Int SCSI Conn Int SCSI Conn Rear USB USB 1 1 Front Panel USB USB 1 1 M RO M B Enabled RJ45 400M T s 100MHz...

Page 14: ...itecture Overview The Intel SHG2 Server Board is designed around the Intel Xeon processor and the ServerWorks Grand Champion LE ServerSet chipset This combination provides the basis for a high performance system with leading edge processor memory and I O performance The SHG2 baseboard architecture provides for two INT3 compliant 603 pin processor sockets supporting dual processing operation using ...

Page 15: ...nstallation of one to two identical Intel Xeon processors Embedded VRMs to support two Xeon processors ServerWorks Grand Champion LE chipset Champion Memory and I O Controller Low End CMIC LE Champion South Bridge CSB5 Champion I O Bridge CIOBX2 Support for 6 DDR registered ECC Synchronous Dynamic RAM SDRAM DIMMs Error Correcting Code ECC single bit correction and multiple bit error detection and ...

Page 16: ...hapter 3 Baseboard PCI I O Subsystem Detailed descriptions of the PCI I O subsystem Three PCI buses are detailed with specifics on embedded devices and provided slots Interrupt routing information is also provided Chapter 4 Clock Generation and Distribution Identification of the clock signals generated and used on the SHG2 server board and detailed drawings of their implementation Chapter 5 Server...

Page 17: ...Intel SHG2 DP Server Board Technical Product Specification Introduction Revision 1 0 Intel Order Number C11343 001 5 Chapter 11 Regulatory and Integration Information ...

Page 18: ...ms and standard high volume SHV servers Dual 603 pin processor sockets that accept the Intel Xeon processors Processor host bus AGTL supported circuitry including termination power supply Integrated APIC signals support Miscellaneous logic for reset configuration processor presence detection ITP port and server management 2 2 Processor Support SHG2 specifically supports Intel Xeon processors from ...

Page 19: ...ection circuitry Server management registers and sensors 2 2 2 1 Reset Configuration Logic On the SHG2 platform the BMC is responsible for configuring the processor speeds The BMC uses the processor speed information derived from the Intel Xeon processor SECC FRU devices to determine the appropriate speed to program into the speed setting device I 2 C based EEPROM Mux The processor information is ...

Page 20: ...ncluding PCI X is directed through the CMIC LE and then through either the CIOB X2 or the CSB5 provided 32 bit 33 MHz PCI bus The CSB5 provides a 32 bit 33 MHz PCI bus The CIOB X2 provides a 64 bit 100 MHz PCI X bus and the 64 bit 133 MHz PCI X bus This independent bus structure allows all three PCI buses to operate concurrently and provides 1 2 GB per second of I O bandwidth 2 2 5 CMIC LE The Cha...

Page 21: ... Interleaving can only take place between identical memory modules Note Although the use of DDR266 modules is supported for upward compatibility the channel throughput is fixed at 400 MT s and the use of higher speed DIMMs will not provide additional bandwidth Mixed memory is not recommended all DIMM sites should be populated with the same speed and when possible same manufacturer 2 3 1 Chipkill T...

Page 22: ...128 MB 256 MB 512 MB 1 GB and 2 GB Serial PD JEDEC Rev 2 0 Voltage Options 2 5 V VDD VDDQ DIMMs must be populated in pairs for a x144 wide memory data path Table 1 Memory DIMM Pairs Memory DIMM DIMM PAIR Row DIMM 1A DIMM 1B 1 1 2 DIMM 2A DIMM 2B 2 3 4 DIMM 3A DIMM 3B 3 5 6 DIMM Pair 3A B DIMM Pair 2A B DIMM Pair 1A B Figure 3 SHG2 Memory Bank Layout ...

Page 23: ... 3 V keyed 64 bit PCI expansion slot connectors numbered PCIX 1 and PCIX 2 supporting 100 MHz 3 3V compliant PCI X adapters and both 66 MHz and 33 MHz 3 3V compliant PCI adapters 2 3 3 2 64 133 MHz I O Subsystem The 64 133 MHz subsystem supports the following embedded device and connector Dual Channel Ultra 160 SCSI Controller Adaptec 7899 SCSI Controller Note When the 7899 is enabled the PCI expa...

Page 24: ...00 synchronous DMA mode transfers 2 4 3 USB Interface The CSB5 contains a USB controller and USB hub The USB controller moves data between main memory and the four USB connectors provided The SHG2 baseboard provides three external USB connector interfaces on the rear I O panel All ports function identically and support the same bandwidth The external connector is defined by the USB Specification R...

Page 25: ...e 2 CSB5 GPIO Usage Table Pad Usage Description V3 CMIC_FATALN CMIC fatal error condition W2 CMIC_ALERTN CMIC error condition W3 SCSI_IDSEL_EN SCSI ID select enable W4 CIOB1_ALERTN CIOB error condition Y4 CSB5_NMI CSB5 NMI condition Y1 BMC_IRQ_SMI 10 BMC SMI condition Y2 LAN1_IDSEL_EN LAN1 ID select enable Y19 NVRAMCLR Non volatile RAM clear status V17 PASSDIS 00 Allows password to be disabled U16...

Page 26: ...board See Section 8 Connections for connector pinout information Upon reset the SIO reads the values on GPO pins to determine its boot up address configuration 2 5 1 1 Serial Ports One 9 pin connector in a D Sub housing is provided for serial port A while serial port B is optional via cable to the rear of the chassis through a 9 pin connector Both ports are compatible with 16450 and 16550A modes a...

Page 27: ... ACK_L 23 GND 11 BUSY 24 GND 12 PE 25 GND 13 SLCT 2 5 1 3 Floppy Port The Floppy Disk Controller FDC is located in the the Super I O controller SIO The SIO is software compatible with the PC8477 which contains a superset of the FDC functions in the uDP8473 NEC uPD765A and N82077 The baseboard provides the 48 MHz clock termination resistors and chip selects All other FDC functions are integrated in...

Page 28: ...round 4 FUSED_VCC 5 V fused 5 MSECLK Mouse Clock 6 NC 2 5 1 5 GPIO The PC PC87417VLA provides several of the GPIO pins that the SHG2 server board utilizes Table 8 identifies the pin the signal name specified in the schematic and a brief description of its usage Table 8 Super I O GPIO Usage Table Pin Usage Descritpion 1 2 3 PKG_SELECT 1 3 PKG ID 5 PCIXCAP1 SW To enable disable pcix mode to slot6 49...

Page 29: ...uct Specification Processor and Chipset Revision 1 0 Intel Order Number C11343 001 17 management events the BMC or the front panel This circuitry is powered from stand by voltage which is present anytime the system is plugged into an AC outlet ...

Page 30: ...upported 64 133MHz 64 bit 133 MHz PCI X 1 slots 64 bit 133 MHz Full length cards supported 32 33MHz 32 bit 33 MHz PCI 3 slots 32 bit 33 MHz Full length cards supported 3 2 64 bit 100MHz PCI X Subsystem 64 100 MHz segment supports these embedded devices and connectors Two 184 pin 3 3 V 64 bit PCI X expansion connectors numbered PCIX 1 64 100 and PCIX 2 64 100 One embedded 82544GC Gigabit Ethernet C...

Page 31: ...thernet LAN component capable of providing 1000 100 and 10 Mbps data rates It is a single chip device containing both the MAC and PHY layer functions The 82544GC utilizes a 64 bit 100 MHz direct interface to the PCI X bus compliant with the PCI Local Bus Specification Revision 1 0a 3 3 64 bit 133MHz PCI X Subsystem A 64 133 MHz segment supports these embedded devices and connectors One dual channe...

Page 32: ...ector LVD interface Each controller has its own set of PCI X configuration registers and SCSI I O registers The AIC 7899 performance levels at 3 3 VIO are as follows When operating in PCI mode as a 64 bit bus master the AIC 7899 can support memory data transfer rates up to 533 GB s at 66MHz and 266MB s at 33MHz When operating in PCI mode as a 32 bit bus master the AIC 7899 can support memory data ...

Page 33: ...nd the ATI RAGE XL controller All PCI masters must arbitrate for PCI access using resources supplied by the CSB5 The host bridge PCI interface CSB5 arbitration lines REQx and GNTx are a special case in that they are internal to the host bridge Table 15 defines the arbitration connections Table 15 32 33MHz Segment Arbitration Connections Baseboard Signals Device D_PCIREQN D_PCIGNTN 32 33MHz Slot PC...

Page 34: ...The SVGA subsystem supports a variety of modes up to 1600 x 1200 resolution in 8 16 24 32 bpp modes under 2D and up to 1024 x 768 resolution in 8 16 24 32 bpp modes under 3D It also supports both CRT and LCD monitors up to 100 Hz vertical refresh rate The SHG2 server board provides a standard 15 pin video graphics array VGA connector and supports disabling of the onboard video through the BIOS Set...

Page 35: ...5 4 2 VGA Connector Table 17 shows the pinout of the VGA connector For more information see the ATI RAGE XL Technical Reference Manual Table 17 Video Port Connector Pinout Pin Signal Description Pin Signal Description 1 RED Analog color signal R 9 VREF Video Power 2 GREEN Analog color signal G 10 GROUND Video ground 3 BLUE Analog color signal B 11 N C No connect 4 N C No connect 12 DDCDAT Monitor ...

Page 36: ...Connection Map PCI IRQ to IRQ 1 3 7 9 12 14 15 SCAN PIRQ PIRQ 0 PIRQ 1 PIRQ 2 PIRQ 3 PIRQ 4 PIRQ 5 PIRQ 6 PIRQ 7 PIRQ 8 PIRQ 9 PIRQ 10 PIRQ 11 PIRQ12 PIRQ13 PIRQ14 PIRQ 15 PCI Interrupts Address Index Register PCI Interrupt Redirection Register IO Address c00h IO Address c01h SCAN IRQ Keyboard Serial Port2 Serial Port1 ESMINT FDD Parallel Port RTC ESMINT ESMINT Mouse FERR Super I O Slot1 intA 2nd ...

Page 37: ...5 PIRQ0 PIRQ1 PIRQ2 PIRQ3 PIRQ4 PIRQ5 PIRQ6 PIRQ7 PIRQ8 PIRQ9 PIRQ10 PIRQ11 PIRQ12 PIRQ13 PIRQ14 PIRQ15 03 02 SLOT 04 06 05 B C D SCI Slot03 INTA Slot06 INTA Slot04 INTA Slot05 INTA Slot02 INTA 01 Timer KB Cascade Connection SIO2 SIO1 Floppy Parallel Mouse RTC S_IDE CoprocessorErr P_IDE VGA SCSI Port A LAN 1 82550 SCSI Port B LAN 2 82544 Slot01 INTA ESMINT ESMINT ESMINT Figure 5 SHG2 Interrupt Rou...

Page 38: ...input of 82559 inside of CSB5 3 6 1 Serialized IRQ support The SHG2 baseboard supports the serialized interrupt delivery mechanism The serialized IRQ SERIRQ consists of a start frame a minimum of 17 interrupt request IRQ data channels and a stop frame Any slave device in quiet mode may initiate the start frame While in the continuous mode the start frame is initiated by the host controller 3 6 2 I...

Page 39: ...d CPU2 the CMIC LE memory buffer and the ITP port 48 MHz at 3 3V logic levels for CSB5 and Super I O 33 3 MHz at 3 3 V logic levels for reference clock for the PCI bus clock driver Other clock sources on the Intel SHG2 server board generates 66 133 MHz at 3 3V logic levels for PCI X Slot 6 and Ultra 160 SCSI 100 MHz at 3 3V logic levels DDR DIMMs PCI X Slot 1 2 and Gigabit 82544GC 40 MHz XTAL for ...

Page 40: ...MHz PCI CLOCK PCI Slot 4 33 MHz PCI Slot 5 CSB5 CIOB X2 33 MHz 33 MHz HOST CLOCK BUFFER 14 318MHz CPU1 CPU2 CMIC LE MEM CLK BUF 100 MHz 100 MHz 100 MHz 100 MHz ITP CSB5 VGA SIO CSB5 SIO 100 MHz 14 MHz 48 MHz 48 MHz HOST CLOCK PCI CLK BUF 33 MHz MEM CLOCK BUFFER DIMM SLOT A1 DIMM SLOT B1 DIMM SLOT A2 DIMM SLOT B2 100 MHz 100 MHz 100 MHz 100 MHz DIMM SLOT A3 DIMM SLOT B3 100 MHz 100 MHz 100 MHz MEM ...

Page 41: ...TFORM MANAGEMENT BUS IPMB Reset Button Chassis Intrusion Power Connector To Power Distribution Board Baseboard Temp 1 Private Management Busses RAM CODE updateable SMI Platform Management Interrupt Routing Non volatile read write storage SENSOR DATA RECORDS SYSTEM EVENT LOG FRU INFO CONFIG DEFAULTS SMM BIOS I F COM 2 COMM MUX BBD COM2 CPU Core Temp 2 EMP DIMM SPD 6 Speaker Power LED Fault Status L...

Page 42: ...tect Table 18 details some of the inputs on the Heceta5 ADM1026 as used on the SHG2 server board Table 18 ADM1026 Input Definition Pin ADM1026 Signal Name Type External Signal Name Function 1 GPIO9 Digital Input CPU2_IERR CPU2 IERR 2 GPIO8 Digital Input CPU1_IERR CPU1 IERR 3 FAN0 GPIO0 Digital Output ADM_DIS_CPU1_L CPU1 Stop Clock 4 FAN1 GPIO1 Digital Output ADM_DIS_CPU2_L CPU2 Stop Clock 5 FAN2 G...

Page 43: ...ion Off Eight bit analog readings for the following system temperatures are provided described in Table 19 Table 19 Temperature Sensors Temperature Sensor Description Resolution Accuracy Primary Processor Primary processor socket thermal sensor 8 bit 5 C or better Secondary Processor Secondary processor socket thermal sensor 8 bit 5 C or better 5 2 System Reset Control Reset circuitry on the Intel...

Page 44: ..._GOOD After 500 ms it is reasserted and the power up reset sequence is completed The Sahalee BMC is not reset by a hard reset It may be reset at power up 5 2 3 Soft Reset A soft reset causes the processors to begin execution in a known state without flushing caches or internal buffers Soft resets can either be generated by SIO KBD_PINITN CSB5 RSB_PINITN or by the CMIC LE CMIC_PINITN PCIRST 32b PCI...

Page 45: ...Connector 5VSB 0x9A IPMB Connector 3VSB TBD Depends on plug in card In addition to the public IPMB the Sahalee BMC also has five private I2 C buses that are used on the baseboard The Sahalee BMC is the only master on the private buses The following tables list all server board connections to the Sahalee BMC private I 2 C buses Table 21 Private I 2 C Bus 1 Devices Function Voltage Address Notes PCI...

Page 46: ... 3 Devices Function Voltage Address Notes Aux Power Connector 3 VSB 0xBC 0xAC 0xB0 0xA0 0xB1 0xA1 0xB2 0xA2 ADM1026 3 VSB 0x58 Table 24 Private I 2 C Bus 4 Devices Function Voltage Address Notes CPU1 3 VSB 0xC0 0x30 CPU2 3 VSB 0xC1 0x31 PC87417 SIO 3 VSB 0x60 Table 25 Private I 2 C Bus 5 Devices Function Voltage Address Notes NIC1 82550PM 3 VSB 0x84 ...

Page 47: ... voltages and assisted gunning transceiver logic AGTL voltage levels Sensors are managed by the BMC The BMC is capable of receiving event messages from individual sensors and logging system events 6 2 Handling and Logging System Errors This section describes actions taken by the SMI handler with respect to the various categories of system errors It covers the events logged by the BIOS and the form...

Page 48: ...ed PXE boot System Boot Initiated A1h 1Dh 04h Automatic boot to diagnostic 00h No bootable media Boot Error A2h 1Eh 02h PXE Server not found 06h CMIC function 0 Errors 07h CMIC function 1 3 Errors Chipset Specific Critical Interrupt A9h F4h 08h CIOBX2 0 Errors Table 27 below describes the various fields in the event request message as sent by the BIOS Regarding the detail refer to the SHG2 Basic I...

Page 49: ...n the case of irrecoverable errors on the host processor bus proper execution of the SMI handler cannot be guaranteed and the SMI handler cannot be relied upon to log such conditions The BIOS SMI handler records the error to the SEL only if the system has not experienced a catastrophic failure that compromises the integrity of the SMI handler The BIOS always enables the error correction and detect...

Page 50: ...g will not inhibit the system from booting 6 4 2 Timestamp Clock The BMC maintains a four byte internal timestamp clock used by the SEL and SDR subsystems This clock is incremented once per second and is read and set using the Get SEL Time and Set SEL Time commands respectively The Get SDR Time command can also be used to read the timestamp clock The BMC has direct access to the system RTC This al...

Page 51: ...timer is disabled to prevent any unprotected window of time Near the end of POST before the option ROMs are initialized the BIOS will disable the FRB 2 timer in the BMC If the system contains more than 1 GB of memory and the user chooses to test every DWORD of memory the watchdog timer is disabled before the extended memory test starts because the memory test can take more than 6 minutes under thi...

Page 52: ...if present 0Ah Cache initialization At beginning of setting up processor cache 0Bh SM Bus initialization At beginning of configuring SMBus to communicate with BMC 0Ch Keyboard controller initialization At keyboard discovery scan 0Dh Embedded controller management controller initialization When first checking for functional BMC 12h Calling operating system wake up vector When waking from Wake On LA...

Page 53: ...Mode 04 Get Processor type 06 Initialize system hardware 08 Initialize chipset registers with initial POST values 09 Set in POST flag 0A Initialize Processor registers 0B Enable Processor cache 0C Initialize caches to initial POST values 0E Initialize I O 0F Initialize the local bus IDE 10 Initialize Power Management 11 Load alternate registers with initial POST values 12 Restore Processor control...

Page 54: ...t CMOS 49 Initialize PCI bus and devices 4A Initialize all video adapters in system 4B Display QuietBoot screen 4C Shadow video BIOS ROM 4E Display copyright notice 50 Display Processor type and speed 52 Test keyboard 54 Set key click if enabled 55 USB initialization 56 Enable keyboard 58 2 2 3 1 Test for unexpected interrupts 5A Display prompt Press F2 to enter SETUP 5C Test RAM between 512 and 6...

Page 55: ...ble A20 address line 95 Install CD ROM for boot 96 Clear huge ES segment register 98 1 2 Search for option ROMs One long two short beeps on checksum failure 9A Shadow option ROMs 9C Set up Power Management 9E Enable hardware interrupts A0 Set time of day A2 Check key lock A4 Initialize typematic rate A8 Erase F2 prompt AA Scan for F2 key stroke AC Enter SETUP AE Clear in POST flag B0 Check for err...

Page 56: ...ors E9 Set 4 GB segment limits EA Perform platform initialization EB Initialize PIC and DMA EC Initialize memory type ED Initialize memory size EE Shadow boot block EF Test system memory F0 Initialize interrupt services F1 Initialize real time clock F2 Initialize video F3 Initialize beeper F4 Initialize boot F5 Restore segment limits to 64 KB F6 Boot mini DOS F7 Boot full DOS 6 5 3 POST Error Code...

Page 57: ...ds cleared 0260 System timer error System timer error 0270 Real time clock error RTC error 0271 Check date and time setting RTC time setting error 02B0 Diskette drive A error 02B2 Incorrect Drive A type run SETUP Incorrect Drive A type 02D0 System cache error Cache disabled CPU cache error 0B00 Rebooted during BIOS boot at Post Code 0B1B PCI System Error on Bus Device Function PCI system error in ...

Page 58: ...ng redundant power module confirmation The error occurred while retrieving the power information 0B80 BMC Memory Test Failed BMC device chip failed 0B81 BMC Firmware Code Area CRC check failed 0B82 BMC core Hardware failure 0B83 BMC IBF or OBF check failed Access to BMC address failed 0B90 BMC Platform Information Area corrupted BMC device chip failed 0B91 BMC update firmware corrupted 0B92 Intern...

Page 59: ...B9h the following message is displayed 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 0 P r e P A r e T o B o o t 1 When POST Error occurs the following message is displayed It displays up to 6 messages as shown below starting on Row0 Column0 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 0 N N N N N N N N N N N N 1 N N N N N N N N N N N N 6 5 4 3 Virtual LCD The BMC implements a virtual LCD tha...

Page 60: ... Number C11343 001 Revision 1 0 48 7 Jumpers 7 1 Hardware Configuration This section describes jumper options on the baseboard The SHG2 server board has 10 jumpers to control various configuration options CN43 CN58 CN53 CN57 CN56 CN27 CN32 CN14 CN47 CN48 Figure 9 Jumper Location ...

Page 61: ...z PCIX2_DIS Secondary Set 66MHz 1 2 Open 3 4 Set 2 4 1 3 SIG SIG GNDGND CN58 1 2 SIDE_CI Chassis Intrusion Detection 1 2 Connected 1 2 GND SIG The following headers will be de featured for production These features are intended for test and evaluation only The headers will not be populated during production CN47 1 2 BMC_FRC_UPDATE Force BMC in update mode 1 2 Open 1 2 SIG GND CN48 1 2 FRB3STP To d...

Page 62: ...all the connector locations 1 A B C D E F G H I J K L M N Figure 10 SHG2 Baseboard Connector Identification and Locations Table 34 SHG2 Baseboard Connectors Key Connector Name ID Key Connector Name ID A SCSI channel A LVDS connector CN54 H Legacy Floppy connector CN31 B SCSI channel B LVDS connector CN55 I Processor 2 socket U36 C HSBP A B connector CN50 CN52 J Processor 1 socket U14 ...

Page 63: ...ugh two primary and one auxiliary power connector The two main power connectors are identified as CN43 and CN42 The auxiliary power connector identified as CN13 provides server management communication with the power supply Table 35 Main Power Connector CN6 Key M Pin Signal Pin Signal 1 3 3V 13 3 3V 2 3 3V 14 12V 3 Common GND 15 Common GND 4 5V 16 DCON 00 5 Common GND 17 Common GND 6 5V 18 Common ...

Page 64: ...ut CN54 CN55 Key A B Connector Contact Number Signal Name Connector Contact Number Signal Name Connector Contact Number Signal Name 1 DT 12 24 ACK 47 DT 7 2 DT 13 25 RST 48 DTP 0 3 DT 14 26 MSG 49 GROUND 4 DT 15 27 SEL 50 GROUND 5 DTP 1 28 C D 51 TERMPWR 6 DT 0 29 REQ 52 TERMPWR 7 DT 1 30 I O 53 RESERVED 8 DT 2 31 DT 8 54 GROUND 9 DT 3 32 DT 9 55 ATN 10 DT 4 33 DT 10 56 GROUND 11 DT 5 34 DT 11 57 ...

Page 65: ...in out of the 34 pin Legacy floppy connector Table 39 Legacy 34 pin Floppy Connector Pin out CN31 Key H Pin Signal Name Pin Signal Name 1 Ground 2 DENSEL 3 Ground 4 Reserved 5 Key 6 DRATE 7 Ground 8 INDEX 9 Ground 10 Motor Enable A 11 Ground 12 Drive Select B 13 Ground 14 Drive Select A 15 Ground 16 Motor Enable B 17 Ground 18 DIR 19 Ground 20 STEP 21 Ground 22 Write Data 23 Ground 24 Write Gate 2...

Page 66: ...et IDE 2 Ground 3 Host Data 7 4 Host Data 8 5 Host Data 6 6 Host Data 9 7 Host Data 5 8 Host Data 10 9 Host Data 4 10 Host Data 11 11 Host Data 3 12 Host Data 12 13 Host Data 2 14 Host Data 13 15 Host Data 1 16 Host Data 14 17 Host Data 0 18 Host Data 15 19 Ground 20 Key 21 DDRQ0 DDRQ1 22 Ground 23 I O Write 24 Ground 25 I O Read 26 Ground 27 IOCHRDY 28 Vcc pull down 29 DDACK0 DDACK1 30 Ground 31 ...

Page 67: ...HDD_LED 10 HDD Activity LED Cathode Low True 10 FP_SYS_FLT_LED 10 Power Fault LED Cathode Low True 11 FP_POWERSW 00 Power Switch Low True 12 LAN1_LINK_LED 10 NIC 1 Activity LED Anode VDC 13 GND Power Switch GROUND 14 LAN1_ACTIVE_LED 10 NIC 1 Activity LED Cathode Low True 15 FP_RESETSW 00 Reset Switch Low True 16 IPMB_DATA 00 I 2 C SDA 17 GND Reset Switch GROUND 18 IPMB_CLK FPD I2C SCL 19 FP_SLEEPS...

Page 68: ... VSS A8 VCC F4 VCC N29 VCC AA10 D54 A9 A26 F5 BPM3 N30 No Connect AA11 D53 A10 A20 F6 BPM0 N31 No Connect AA12 VCC A11 VSS F7 VSS P1 No Connect AA13 D48 A12 A14 F8 BPM1 P2 VCC AA14 D49 A13 A10 F9 GTLREF P3 VSS AA15 VSS A14 VCC F10 VCC P4 VCC AA16 D33 A15 Reserved F11 BINIT P5 VSS AA17 VSS A16 Reserved F12 BR1 P6 VCC AA18 D24 A17 LOCK F13 VSS P7 VSS AA19 D15 A18 VCC F14 ADSTB1 P8 VCC AA20 VCC A19 A...

Page 69: ...S G26 VCC T2 VCC AB19 D14 B18 A5 G27 VSS T3 VSS AB20 D12 B19 REQ0 G28 VCC T4 VCC AB21 VSS B20 VCC G29 VSS T5 VSS AB22 D13 B21 REQ1 G30 No Connect T6 VCC AB23 D9 B22 REQ4 G31 No Connect T7 VSS AB24 VCC B23 VSS H1 No Connect T8 VCC AB25 D8 B24 LINT0 H2 VSS T9 VSS AB26 D7 B25 PROCHOT H3 VCC T23 VSS AB27 VSS B26 VCC H4 VSS T24 VCC AB28 SM_EP_A2 B27 VCCSENSE H5 VCC T25 VSS AB29 SM_EP_A1 B28 VSS H6 VSS ...

Page 70: ... No Connect V8 VCC AC30 No Connect C29 VSS K2 VSS V9 VSS AC31 No Connect C30 No Connect K3 VCC V23 VSS AD1 Reserved C31 No Connect K4 VSS V24 VCC AD2 VCC D1 No Connect K5 VCC V25 VSS AD3 VSS D2 VSS K6 VSS V26 VCC AD4 VCCIOPLL D3 VID2 K7 VCC V27 VSS AD5 TESTHI5 D4 STPCLK K8 VSS V28 VCC AD6 VCC D5 VSS K9 VCC V29 VSS AD7 D57 D6 INIT K23 VCC V30 No Connect AD8 D46 D7 MCERR K24 VSS V31 No Connect AD9 V...

Page 71: ... VSS M8 VSS Y15 DSTBN2 AE12 DBI2 E10 AP0 M9 VCC Y16 VCC AE13 D35 E11 BR2 M23 VCC Y17 DSTBP1 AE14 VCC E12 VCC M24 VSS Y18 DSTBN1 AE15 Reserved E13 A28 M25 VCC Y19 VSS AE16 Reserved E14 A24 M26 VSS Y20 DSTBP0 AE17 DP3 E15 VSS M27 VCC Y21 DSTBN0 AE18 VCC E16 COMP1 M28 VSS Y22 VCC AE19 DP1 E17 VSS M29 VCC Y23 D5 AE20 D28 E18 DRDY M30 No Connect Y24 D2 AE21 VSS E19 TRDY M31 No Connect Y25 VSS AE22 D27 ...

Page 72: ...isy chained cabling Additional information about the ICMB can be found in the External Intelligent Management Bus Bridge External Program Specification Table 43 ICMB Connector Pin out ICMB Key N Pin Name 1 XP05S 2 ICMB_TX 3 ICMB_TX_ENB 4 ICMB_RX 5 GND 8 8 2 Auxiliary I2C Connector IPMB CN44 Key D The baseboard provides a 3 pin auxiliary I 2 C connector for OEM access to the IPMB This connector is ...

Page 73: ...wo fan connectors are for back of chassis and four connectors on the baseboard attach to chassis fans equipped with a sensor that indicates whether the fan is operating The chassis fans can also be turned on and off from the BMC The sensor pins for all of these fans are routed to the BMC for failure monitoring Figure 11 shows the fan connector locations on the SHG2 server board and indicates the c...

Page 74: ...er Number C11343 001 Revision 1 0 62 FAN 1 FAN 3 FAN 5 FAN 4 FAN 2 Fan headers Figure 12 SHG2 System Redundant Cooling Fan Support FAN 1 to CN23 FAN 3 to CN41 FAN 5 to CN28 FAN 4 to CN46 FAN 2 to CN22 I O Cooling Zone Core Cooling Zone CN 1 CN 18 CN 23 CN 22 CN 28 CN 36 CN 41 CN 46 ...

Page 75: ...N46 92 x 25mm Fan 4 not used CPU1 Fan CN1 PWT and fans not used 60 x 25mm Processors PWT CPU2 Fan CN18 PWT and fans not used 60 x 25mm Note For the KHD3HSRP650 Chassis processor cooling is implemented via ducted Fans 1 2 5 in the core cooling zone rather than using processor wind tunnels PWT The two 80 x 32mm KHD3BASE450 fans can be connected to any of the four front fan headers 8 9 1 Fan Connecto...

Page 76: ...el also referred to as the back panel Note The orientation of the RJ45 connectors for NIC and NIC2 are inverted with respect to one another tab up and tab down The intial production release boards will ship with connectors oriented in this fashion A post production ECO is planned to change the orientation of these connectors Table 47 lists and identifies each of the connectors D A B C E F G H I J ...

Page 77: ...ore devices are required an external hub can be connected to either the back panel ports or the on board header Table 48 USB Connector Key A B C Pin Signal USB Connector 1 Port A USBP1_VCC Fused VCC 5V with over current monitor of port 0 1 and 2 2 Port A USB_P1_N Differential data line paired with USB_P1_P 3 Port A USB_P1_P Differential data line paired with USB_P1_N 4 Port A USBP1_GND 5 Port B US...

Page 78: ...on Pin Signal Description 1 MSDATA Mouse Data 1 KBDATA Keyboard Data 2 GND Ground 2 GND Ground 3 GND Ground 3 GND Ground 4 MSFUSE 5V 4 KBFUSE 5V 5 MSCLK Mouse clock 5 KBCLK Keyboard clock 6 GND Ground 1 2 6 4 3 5 6 GND Ground 8 10 3 Serial Ports Key F L The SHG2 server board provides one RS 232C serial port and a second serial port available through an onboard header Key L The back panel serial po...

Page 79: ... 00_2 carrier detect 2 SIODSR 00_2 data set ready 3 SIORXD 00_2 receive data 4 SIORTS 00_2 request to send 5 SIOTXD 00_2 transmit data 6 SIOCTS 00_2 clear to send 7 SIODTR 00_2 data terminal ready 8 SIORI 00_2 ring indicator 9 GROUND 10 KEY 8 10 4 Parallel Port The IEEE 1284 compatible parallel port used primarily for a printer sends data in parallel format The parallel port is accessed through a ...

Page 80: ...0 8 10 6 Ethernet Connectors Key I J The system supports two onboard network interface controllers one 10 100 Mbps NIC 1 and one 10 100 1000 Mbps NIC 2 These Ethernet connectors are each single RJ 45 connectors with integrated activity link and speed status LEDs Table 55 Ethernet Connectors Key I J Pin NIC1 Signal 10 100 NIC2 Signal 10 100 1000 Ethernet Connectors 1 L1TD TR0 2 L1TD TR0 3 GND TR1 4...

Page 81: ...e transmit receive activity on the LAN a valid link to the LAN and 10 or 100 or 1000 Mbps operation The single green LED indicates network connection when illuminated and TX RX activity when blinking When the SPEED LED is not illuminated it indicates network connection at10 Mbps operation When the SPEED LED is illuminated in green it indicates network connection at100 Mbps operation Amber illumina...

Page 82: ...HIELDE 1 VESA Video Foxconn Electronics Inc DZ11A36 R9 CONN I O 9P DSUB RA 109 062ST 1 Serial 1 Comm Foxconn Electronics Inc DT10126 R9 CONN I O 25P DSUB RA 109 093ST 1 Parallel Comm Foxconn Electronics Inc DM11356 R1 CONN I O 16P RJ45 USB RA 0 1 062ST 1 NIC 1 with integrated Activity LED Tyco Electronics Corporation 1116151 2 CONN I O 12P DIN RA 0 1 093ST 1 Tyco Electronics Corporation 84405 1 St...

Page 83: ...43051302 CONN HDR 2 X 12 PLG VT 0 1 062ST KP 3 1 SSI Front Panel Foxconn Electronics Inc HC1912G D5 CONN HDR ST PLRZ 2X 4 P 1 Foxconn Electronics Inc HC1904G D0 Extended Front Panel Tyco Electronics Corporation 2 146220 1 CONN HDR 1 X 2 PLG VT 0 1 093ST KP PG 1 Intrusion Switch Header Foxconn Electronics Inc HF06021 P1 Stacked USB Port 1 2 and 3 Foxconn Electronics Inc UB1112C M1 1 ICMB Four Posit...

Page 84: ...ectrical and Thermal Specifications Operating Temperature 5 C to 50 C 1 Storage Temperature 55 C to 150 C Voltage on any signal with respect to ground 0 3V to Vdd 0 3V 2 3 3V supply voltage with respect to ground 0 3 to 3 63V 5V supply voltage with respect to ground 0 3 to 5 5V Notes 1 Chassis design must provide proper airflow to avoid exceeding Intel Xeon IHS integrated heat spreader maximum cas...

Page 85: ...cations DC and AC specifications for the SHG2 server board are summarized here 9 3 1 Power Consumption Table 62 shows the power consumed on each supply line for a SHG2 baseboard configured with two processors each a 65W maximum and 2 DIMMs stacked burst with 4 DIMMs in standby at 70 maximum Note The following numbers are provided as an example Actual power consumption will vary depending on the ex...

Page 86: ...operation The output voltages must rise from 10 to within regulation limits Tvout_rise within 5 to 70ms The 3 3 V 5 V and 12 V output voltages should start to rise approximately at the same time All outputs must rise monotonically The 5 V output needs to be greater than the 3 3 V output during any point of the voltage rise The 5 V output must never be greater than the 3 3 V output by more than 2 2...

Page 87: ...n Off Timing Item Description Min Max Units Tsb_on_delay Delay from AC being applied to 5VSB being within regulation 1500 msec T ac_on_delay Delay from AC being applied to all output voltages being within regulation 2500 msec Tvout_holdup Time all output voltages stay within regulation after loss of AC 21 msec Tpwok_holdup Delay from loss of AC to deassertion of PWOK 20 msec Tpson_on_delay Delay f...

Page 88: ...gulation to O Ps being in regulation at AC turn on 50 1000 msec Figure 16 Turn On Off Timing 9 3 2 2 Voltage Recovery Timing Specifications The power supply must conform to the following specifications for voltage recovery timing under load changes 1 Voltage shall remain within 5 of the nominal set voltage on the 5 V 12 V 3 3 V 5 V and 12 V outputs during instantaneous changes in load shown in the...

Page 89: ...The combined error of peak overshoot set point regulation and undershoot voltage shall be less than or equal to 5 of the output voltage setting The transient response measurements shall be made with a load changing repetition rate of 50Hz to 5kHz The load slew rate shall not be greater than 0 2A µs Table 67 Transient Load Requirements Output Step Load Size Load Slew Rate Capacitive Load 3 3V 25 of...

Page 90: ...mber C11343 001 Revision 1 0 78 10 Mechanical Specifications The following diagrams show the mechanical specifications of the SHG2 server baseboard All dimensions are given in inches and are dimensioned per ANSI Y15 4M Connectors are dimensioned to pin 1 Figure 17 SHG2 Baseboard Mechanical Diagram 1 ...

Page 91: ...Intel SHG2 DP Server Board Technical Product Specification Mechanical Specifications Revision 1 0 Intel Order Number C11343 001 79 Figure 18 SHG2 Baseboard Mechanical Diagram 2 ...

Page 92: ...erification Radiated Conducted Emissions USA ICES 003 Class A Radiated Conducted Emissions Canada CISPR 22 3 RD Edition Radiated Conducted Emissions International AS NZS 3548 Class A Radiated Conducted Emissions Australia New Zealand RRL MIC Notice 1997 42 Radiated Conducted Emissions Korea BSMI CNS13438 Radiated Conducted Emissions Taiwan 11 1 3 Product Regulatory Compliance Markings This product...

Page 93: ...cated on solder side of the server board 11 3 Replacing the Back up Battery The lithium battery on the server board powers the RTC for up to 10 years in the absence of power When the battery starts to weaken it loses voltage and the server settings stored in CMOS RAM in the RTC for example the date and time may be wrong Contact your customer service representative or dealer for a list of approved ...

Page 94: ...sfara vid felaktigt batteribyte Använd samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren Kassera använt batteri enligt fabrikantens instruktion VAROITUS Paristo voi räjähtää jos se on virheellisesti asennettu Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiin Hävitä käytetty paristo valmistajan ohjeiden mukaisesti ...

Page 95: ...ller bridge DDR SDRAM Double Data Rate SDRAM DIMM Dual Inline Memory Module DMTF Distributed Management Task Force DP Dual processor DRAM Dynamic Random Access Memory EMC Electromagnetic Compatibility EMI Electromagnetic Interference EMP Emergency Management Port FMB Flexible Motherboard FRB Fault Resilient Booting FSB Front Side Bus GPI General Purpose Input GPIO General Purpose I O GPO General P...

Page 96: ... Real Time Clock SEC Single Edge Contact SEL System Event Log SERIRQ Serialized IRQ SDRAM Synchronous Dynamic RAM SHV Standard High Volume SIO Super I O bridge SM Server Management SMI System Management Interrupt SMM Server Management Module SMT Surface Mount Technology SVGA Super Video Graphics Array TAP Test Access Port TBD To Be Determined Thin IMB Thin Intra Module Bus USB Universal Serial Bus...

Page 97: ...endum to the PCI Local Bus Specification Rev 1 0a USB Specification Revision 1 1 SHG2 Basic Input Output System BIOS External Product Specification Revision 0 5 Intel reference number OR xxxx 3 Volt Flash File 29LV800TAx8 Datasheet PCI Bus Power Management Interface Specification AIC 7899 PCI Bus Master Dual Channel Ultra160 Embedded SCSI ASIC Data Book AIC 7902 PCI X Bus Master Dual Channel Ultra...

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